FPGA and GPU analog analysis

What is FPGA? What is his role? This article compares with GPU to understand some difficult points of FPGA and answers some common questions about FPGA-what is FPGA, why do I need FPGA, how to program FPGA? FPGA( Field Programmable Gate Array) is an important category in integrated circuits. It is called the four general-purpose integrated circuit chips together with CPU, memory and DSP.

FPGAs are a bunch of transistors, and you can wire them up to make any circuit you want. It is like a nano-sized breadboard. Using FPGA is like chip streaming, but you only need to buy this chip to build a different design. In exchange, you need to pay some efficiency.

This statement is literally wrong, because you don't need to rewire the FPGA, it is actually a 2D grid of lookup tables connected by a routing network, as well as some arithmetic units and memory. FPGAs can simulate arbitrary circuits, but they are actually just mimicking, just like software circuit emulators simulate circuits. What makes this answer inappropriate is that it oversimplifies the way people actually use FPGAs. The next two definitions can better describe the FPGA.

Circuit simulation is the classic mainstream use case for FPGAs, which is why FPGAs appeared very early. The key to FPGA is that the hardware design is coded in HDL format, and buying some cheap hardware can get the same effect as ASIC. Of course, you can't use the exact same Verilog code on the FPGA and the real chip, but at least their abstract scope is the same.

This is a different use case than ASIC prototyping. Unlike circuit simulation, computational acceleration is an emerging use case for FPGAs. This is why Microsoft has successfully accelerated search and deep neural networks. And crucially, the calculation example does not depend on the relationship between the FPGA and the real ASIC: the Verilog code written by developers for FPGA-based acceleration does not need to have any similarity to the Verilog code used for tape-out.

These two examples have huge differences in programming, compilers, and abstraction. I pay more attention to the latter, I call it "computaTIonal FPGA programming". My argument is that the current programming methods for computing FPGAs all draw on traditional circuit simulation programming models, which is wrong. If you want to develop ASIC prototypes, Verilog and VHDL are the right choices. But if the goal is computing, we can and should rethink the entire stack.

Let's talk straight away. FPGA is a very special kind of hardware, which is used to efficiently execute the special software described by analog circuits. FPGA configuration requires some low-level software—it is a program written for ISA.

Here you can use the GPU as an analogy.

Before deep learning and blockchain became popular, there was a period when GPUs were used to process graphics. At the beginning of the 21st century, people realized that they would also use GPUs as accelerators when dealing with computationally intensive tasks without graphics data: GPU designers have built more general-purpose machines, and 3D rendering is just one application.

Definition of FPGA and analogy with GPU

The computing FPGA follows the same trajectory. Our idea is to use this fashionable hardware more, of course, not for circuit simulation, but to use the calculation mode suitable for circuit execution, and look at the GPU and FPGA in an analogous manner.

In order for GPUs to develop into today's data parallel accelerators, people have to redefine the concept of GPU input. We used to think that GPUs accepted strange, strong, and domain-specific visual effects descriptions. We implemented GPU execution programs, thereby unlocking their true potential. Such an implementation allows the goal of the GPU to evolve from a single application domain to the entire computing domain.

I think that computing FPGAs are in a similar transition, and there is no concise description of the basic computing modes that FPGAs are good at. But it is related to potentially irregular parallelism, data reuse, and most static data flows.

Like GPUs, FPGAs also need hardware abstractions that can embody this computing model. The problem with Verilog for computing FPGAs is that they do not perform well in low-level hardware abstractions or in high-level programming abstractions. Let us imagine through the counter-evidence method what it would be like to replace these roles with RTL (register transfer level).

Even RTL experts may not believe that Verilog is a way to efficiently develop mainstream FPGAs. It does not push programming logic to the mainstream. For experienced hardware hackers, RTL design seems to be friendly and familiar, but the productivity gap between it and the software language is immeasurable.

In fact, for current computing FPGAs, Verilog is actually ISA. The main FPGA vendor tool chain will take Verilog as input, while the high-level language compiler will take Verilog as output. Vendors generally keep the bitstream format confidential, so Verilog will be placed as low as possible in the abstract hierarchy.

The problem with using Verilog as an ISA is that it is too far away from the hardware. The abstraction gap between RTL and FPGA hardware is huge. From a traditional perspective, it must at least include synthesis, technology mapping, and place and route-each of which is a complex and slow process. Therefore, the compilation/editing/running cycle of RTL programming on FPGAs takes hours or days. To make matters worse, this is an unpredictable process. The deep stack of the tool chain may obscure changes in RTL, which may affect Design performance and energy characteristics.

A good ISA should directly show the real situation of the underlying hardware without modification. Like assembly language, it doesn't need to be very convenient for programming. But like assembly language, its compilation speed needs to be very fast, and the results are predictable. If you want to build higher-level abstractions and compilers, you need a low-level goal that will not be unexpected. RTL is not such a goal.

If the computing FPGA is an accelerator for a specific type of algorithm mode, then current FPGAs cannot ideally achieve this goal. Under this game rule, a new type of hardware that can defeat FPGAs can bring a new level of abstraction. The new software stack should discard the legacy problems of FPGA in circuit simulation and RTL abstraction. The above is the analysis of FPGA, I hope to help you.