Design of remote display system based on FPGA

LVDS interface, also known as RS-644 bus interface, is a data transmission and interface technology that appeared in the 1990s. LVDS is a small-amplitude differential signal technology that uses very low-amplitude signals (approximately 350 mV). It transmits data through a pair of differential PCB traces or balanced cables. Its single channel transmission rate can reach hundreds of megabits per second. Its unique low-amplitude and constant current source driving method only produces extremely low noise, and its power consumption is very small. The transmission medium can be a copper PCB connection or a balanced cable.

LVDS technology is compared with other interfaces. It has great advantages, mainly in the following aspects:

(1) High rate

Because the voltage change between the LVDS logic states is only 300mV, the state can be changed very quickly, thereby achieving a high rate.

(2) Low power consumption

As the operating frequency increases, the power supply current of LVDS remains flat, while the power supply current of CMOS and TTL technology will increase exponentially with the increase of frequency, which benefits from the use of constant current line drivers. The current source of LVDS can limit the output current to about 3.5mA, and can also limit any spike current generated during the transition. In this way, high data rates of up to 1.5 Gbps are obtained without significantly increasing power consumption. The constant current drive output can also tolerate short circuit or grounding of the transmission line without thermal problems. Because LVDS reduces the termination resistor voltage drop, it also reduces the total power consumption of the circuit.

(3) Good noise performance

The electromagnetic interference generated by LVDS is very low because of the low voltage swing, low edge rate, odd mode differential signal, and constant current driver. Its Icc peak produces only very low radiation. By reducing the voltage swing and current energy, LVDS can reduce the field strength to a minimum; its differential driver also introduces odd mode transmission, which means that equal amounts of current in opposite directions are transmitted on the transmission line. To form a current loop. Therefore, the current loop produces the lowest electromagnetic interference; in the transmission of differential signals, because the differential receiver only responds to the difference between the positive and negative inputs, when the noise appears in both inputs, the amplitude of the differential signal is not affected .

(4) With fail-safe features

Since the constant current drive does not cause any damage to the system, the LVDS driver can be plugged and unplugged with power on. Another feature of LVDS is the fault protection function of the receiver. The LVDS receiver provides a reliable circuit internally. Therefore, it can ensure the reliable output (the convention is "1") when the receiver input is floating, short-circuited, and the receiver input is in the driver tri-state output or the driver power supply is terminated, so as to prevent the output from oscillating.

(5) Strong integration ability

Since high-speed LVDS can be realized in a standard CMOS process, it is very advantageous to use LVDS analog circuits to integrate complex digital functions.

Based on the many advantages of LVDS technology. There are more and more circuit modules for LVDS. This article's LVDS serializer/deserializer MAX9205/MAX9206 is one of the most typical pair of devices.

2. Overview of MAX9205 and MAX9206

MAX9205 and MAX9206 are a group of differential signal chipsets launched by Meixin. Among them, MAX9205 can convert 10-bit parallel COM data or TTL data into a high-speed serial data stream with an embedded clock; MAX9206 is a deserializer that can receive the serial data stream and convert them into parallel data. At the same time, the parallel clock can be rebuilt. The device group uses an embedded clock for data conversion, which can effectively solve the bottleneck problem that restricts the high-speed transmission due to the incomplete synchronization of the clock and data.

2.1 Working principle of MAX9205 and MAX9206

The MAX9205 LVDS serializer and MAX9206 LVDS deserializer can transmit high-speed data over a serial point-to-point link with a differential characteristic impedance of 100 Ω. The parallel clock frequency range of MAX9205 and MAX9206 is 16～40 MHz. During data conversion, two data bits are automatically added inside the serializer element, that is, a start bit (1) and a stop bit (0) are added to the 10-bit data fed in parallel. The output of the liner forms a 12-bit serial data stream, and while the deserializer receives data, it restores the parallel clock frequency according to the rising edge between the stop bit and the start bit of the received data.

2.2 Working mode of MAX9205/MAX9206

The MAX9205 and MAX9206 have four working states: initialization, synchronization mode, data transmission mode and power saving mode. Now they are introduced as follows:

(1) Initialization

After power-on, the output of each pin is in a high-impedance state. After that, the phase-locked loop starts to work and follows the local clock. Once the clock signal is latched, you can prepare to send data signals.

(2) Synchronous mode

The MAX9205 has two synchronization mode selection bits SYNC1 and SYNC2. After initialization, you can decide whether the chip is in synchronization mode or data transmission mode according to the status of these two bits. When one of the two pins lasts for 6 cycles of high state, the chip will transmit 1024 cycles of synchronization signal. The synchronization signal is a serial data stream composed of 6 consecutive 0s and 6 consecutive 1s.

(3) Data transmission mode

After the initialization is completed, if the synchronization pins are all 0. Then data transmission. At this time, the serializer strobes the input data with the TCLK terminal and stores it in the 10-bit input latch. Take out the data from it when sending, and add the start bit (1) and the stop bit (0) of the embedded clock to send a total of 12 bits to the serial differential port in sequence, and then the deserializer will receive The received serial data is converted into 10-bit parallel data and stored in the output latch. At the same time, the parallel clock is recovered and reconstructed from the embedded clock, and the clock is used to gate the output latch and output data.

(4) Power saving mode

Both serializer and deserializer can work in power saving mode. When there is no data transmission, the chip can be put into power saving mode by setting the pin pwden. At this time, the PLL stops working, the output is tri-stated, and the current is reduced to a few milliamps.

3. Realization of remote high-speed data transmission system

In high-speed remote data transmission, the transmission quality of the signal is a test standard for the effectiveness of the entire system. Due to the rapid conversion of high-frequency signals, coupled with external noise and attenuation of the transmission line and the limitations of the device itself, high-speed data systems Design has always been a difficult problem in engineering. Considering these factors comprehensively, this system adopts the method of serializer/deserializer to design the data transmission.