Design of PCI data acquisition card based on FPGA

Discusses the design of PCI data acquisition card based on FPGA. The board realizes query, interrupt and DMA to read data in many ways. It can collect data in real time and realize the cache of large-capacity data. It also effectively solves the problem of high-speed data acquisition, For transmission requirements, the design uses FPGA to implement data acquisition control logic, which reduces the development cycle, and can modify the design and upgrade the design online.

The emergence of digital signal processing has changed the information and signal processing technology, and data acquisition as the preliminary work of digital signal processing, plays a key role in the entire digital system.

1 Data acquisition system

Data collection refers to the process of automatically collecting information from the device under test. Figure 1 shows the components of a typical data acquisition system based on a PC.

PC is selected as the control system operation platform. In order to communicate with external devices, PC provides external USB, serial port, parallel port and built-in ISA, PCI and other interfaces. The PCI bus interface is fast, the system occupancy rate is low, and there is a complete plug-and-play management system, which is the de facto standard for computer plug-in peripheral buses. In this paper, FPGA is used to communicate with the computer through the PCI interface chip, FPGA is connected to the FIFO memory, and the A/D conversion data is directly stored in the FIFO, which realizes high-speed data collection and continuous stable data stream output.

2 Data acquisition hardware design

2.1 PCI bus interface design

The PCI bus is a bus multiplexed with address/data and command/byte selection signals. It uses the master-slave signal two-way handshake to control the data transmission. Its interface circuit design is quite different from the traditional bus interface circuit design, so it must strictly abide by the technical specifications stipulated by the PCI bus specification. This article uses PC19054 of PLX Company as the interface controller of PCI bus. PCI9054 is a dedicated PCI interface chip, which mainly converts complex PCI timing to simple timing.

2.2 FPGA design

The FPGA design is implemented with Very High Speed Integrated Circuit hardware description language (VHDL), and the design software is Quartus II. VHDL design is mainly divided into: bus read-write design, A/D control design, D/A control design, timing/counter design and DIO design.

2.2.1 Bus read-write design

The bus read-write design is the top-level module of FPGA design, which mainly completes the communication between PCI9054 and local to realize the correct transmission of data. State 0 is the idle state, state 1 is the bus hold state, state 2 is the DMA read state, state 3 is the single-cycle write state, and state 4 is the read and write operation completion state.

2.2.2 Description of control signals

ADS#: Address strobe signal, bidirectional. Indicates that the address is valid and the beginning of a new bus access cycle is valid for the first clock cycle around the bus access. BLAST#: Burst transmission end signal, bidirectional. Driven by the active side of the current local bus to indicate the last data transfer on the bus. LW/R#: write/read signal, bidirectional. Read low, write high. LHOL D: Keep the bus request, output. Request to use the local bus. When control can be achieved, the local bus arbitration responds to LHOLDA.

2.2.3 A/D control design

A/D control is the main part of the data acquisition card. The design mainly includes: generation of A/D sampling clock, group acquisition control, trigger setting and FIFO read and write control.

(1) Generation of A/D sampling clock. The generation of the sampling clock is mainly to generate a signal with a certain low pulse width according to the set sampling frequency, which is to correctly read the conversion data when the conversion is completed. It is worth noting that, in the case of FIFO overflow and the interval between group acquisitions, the output pulses should be stopped.

(2) Group collection control. The packet acquisition is designed separately according to the internal and external clock sources. First calculate the total number of points to be collected in a group according to the group cycle times and the first and last channel settings, that is: the total number of points to be collected in a group = (last channel-first channel +1) * group cycle times.

In the internal clock mode, after the A/D conversion is started, the number of acquisition points increases by 1 after each conversion is completed, until the total number of acquisition points within a group is added. At this time, the output of the conversion pulse is stopped, and then the interval between group inputs is entered. Start counting the reference clock, output the conversion pulse after counting the set interval between groups, enter the conversion count cycle again, and repeat accordingly.

In the external clock mode, when the falling edge of the external clock is detected, the conversion pulse is output and counted after the conversion is completed, until the total number of points to be collected within a group is added, then the output of the conversion pulse is stopped, and the external clock appears again When the falling edge of, starts a new group of group acquisition.

(3) Trigger settings. The trigger setting is determined according to the trigger source, trigger direction and trigger type in the control word of the board.

(4) FIFO read and write control. The FIFO read is initiated by PCI9054. In the PCI9054 read cycle, the FIFO read signal is generated and the A/D data is transmitted to the host when the address conditions are met.

The FIFO write signal is controlled by the STS signal of the A/D chip. When the STS signal changes from high to low, this conversion is completed, and the data on the data line is valid, and the FIFO starts the write cycle on the falling edge, and the rising edge The data is entered into the FIFO, so it is only necessary to invert the STS signal and assign it to the FIFO write signal.

3 Testing of hardware design

In the design process of the board, the hardware design test is carried out as follows: first, most of the errors in the design are eliminated through functional simulation and timing simulation; second, the PCItr ee software is used for testing, and simple functional tests, such as switches Volume input and output; then passed the simple demonstration program test; and finally passed the comprehensive test of the advanced program. Various design problems will be discovered in different test stages, and then the design will be returned to functional simulation and timing simulation, and the program will be revised and improved repeatedly until the functional design requirements are finally met.

4 Conclusion

This paper completes the design of the PCI-based data acquisition card based on FPGA. The board implements query, interrupt, and DMA to read data in multiple ways. It can collect data in real time, realize large-capacity data cache, and effectively solve Transmission needs. It can be directly inserted into any PCI slot in a PC or a computer compatible with it to form a data acquisition, waveform analysis and processing system in various fields, and can also form an industrial production process monitoring system.