Design of Multi-phase Frequency Conversion Controller Based on DSP+FPGA

In the application of the motor drive system, the multi-phase motor drive system can be applied to the occasions where the power supply voltage is limited.

Its functions are: 

(1) to solve the problem of low voltage and high power;

(2) to reduce vibration and noise. As the number of motor phases increases, the output torque ripple decreases and the ripple frequency increases, which greatly improves the low-speed characteristics of the drive system; 

(3) improves reliability. Due to the redundancy of the number of phases, when one or even several phases fail in the multi-phase motor drive system, the motor can still run. Therefore, the multi-phase motor drive system is particularly suitable for occasions with high reliability requirements. These advantages of the multi-phase system have aroused widespread concern in the academic and engineering circles. Because the multi-phase system has many switching devices and the control system is complex, the performance requirements of the multi-phase system controller are high.

In the three-phase frequency conversion control system, although the DSP control algorithm has a complex structure, the characteristics of high operation speed, flexible addressing mode and powerful communication performance have been widely used. For multi-phase variable frequency control systems, the controller also requires high real-time performance, can handle a large amount of data, and more interfaces for PWM drive signals, and these requirements can be met by FPGA.

Therefore, based on the three-phase PWM signal generation method, this paper proposes a multi-phase PWM signal generation method based on DSP and FPGA. This method is used to design a multi-phase frequency conversion controller, which has certain versatility, and can be used to set the phase number, modulation waveform and control method online through the host computer software.

1 Design idea of multi-phase inverter controller

The versatility of the multi-phase inverter controller is as follows:

(1) the phase number of the multi-phase motor is optional;

(2) the carrier frequency is optional; 

(3) different modulation waves can be selected according to the needs of harmonic injection; 

(4) Depending on the motor connection, different control methods can be selected.

In order to realize the above-mentioned function, this text adopts the modular method to design the structure of the controller, the controller is made up of three parts of upper computer, DSP and FPGA, its overall structural block diagram is shown as in Fig. 1.

The operating software of the host computer is realized by object-oriented software. From the control panel, the motor can be controlled to run and stop, and the number of motor phases, carrier frequency, modulated wave waveform, dead time, etc. can be set.

In order to maximize the respective advantages of DSP and FPGA, DSP mainly implements the control algorithm, collects feedback signals and communicates with the host computer; FPGA implements the modulation algorithm and generates multi-phase PWM signals. This part takes up more hardware resources and more Real-time requirements are high.

The control process is as follows:

(1) The host computer is connected to the DSP through a serial interface, and sends instructions to the DSP when action is required.

(2) The DSP calls related functions according to the received instructions, such as initializing the system, running the corresponding control algorithm, and collecting signals.

(3) Through the parallel communication between the DSP and the FPGA, the DSP initializes the modulation algorithm of the FPGA and lifts the PWM blockade. The FPGA calculates according to the received frequency and amplitude, and generates a PWM signal.

2 Multiphase PWM waveform generation

2.1 SPWM waveform generation principle

The generating principle of sine pulse width modulation (SPWM) is shown in Figure 2. A set of isosceles triangle waves is compared with a sine wave, and its intersection is used as the rising or falling time of the SPWM wave. When the amplitude of the sine wave is greater than the amplitude of the triangular wave, the output is high level; when the amplitude of the sine wave is less than the amplitude of the triangular wave, the output is low level.

The basic principle of generating SPWM using FPGA is to compare the digital signal generated by the triangular wave generator with the sine wave signal stored in ROM, and determine the output of SPWM wave according to the size of the two.

2.2 Multiphase PWM waveform generation

Figure 3 shows how to generate a three-phase SPWM signal. The function of the sequencer is to generate clock signals of phase A, phase B, and phase C in sequence; address synthesis and data separation utilize the principle of time-division multiplexing, and the purpose is to reduce the number of ROMs used. Only one ROM is needed for the polyphase sine wave, which also creates conditions for the external ROM.

On the basis of the three-phase SPWM signal generation method, this paper proposes a method based on DSP and FPGA that can generate any number of phases and arbitrary waveforms (that is, modulation waveforms), as shown in Figure 4.

The phase register holds the information of the shift angle between the modulation waves of each phase (such as 120° for three phases), so the setting of the phase register is a necessary step to realize the multi-phase PWM signal.

Modulated wave control unit is the core part of realizing multi-phase PWM signal. The function of this part is similar to the sequence generator, address synthesis and data separation part in Figure 3, but there are the following differences:

(1) The phase shift between the generated modulated waves can be freely changed by setting the phase register, while the phase shift in FIG. 3 is fixed and cannot be changed online.

(2) The three-phase modulated wave signal is required to form a group of modulated wave generators (as shown in Figure 3), and the modulated wave control unit is composed of multiple groups of modulated wave generators. The phase shift of the corresponding phase difference between the groups is Can be set. For example, when controlling dual three-phase motors, the phase shift within the group is usually set to 120°, and the phase shift between groups is set to 60° or 30°.

The function of the modulated wave memory is similar to the sine wave ROM in Figure 3, which stores the sine wave calculated by the DSP or the modulated wave wave with harmonics. After each power-on of the controller, the DSP must initialize the modulation wave memory and download the modulation wave table calculated by the DSP to the modulation wave memory.

The amplitude register stores the amplitude and frequency of the modulation wave. The amplitude and frequency are calculated by the DSP in each control cycle. The carrier frequency of the carrier generator (ie, triangle wave generator) is adjustable online; the dead zone register stores the current dead zone value, which can also be changed online. The blocking protection unit is used to block the PWM output signal and protect the main circuit when the system fails.

Because the digital signals in each register or memory are generated by DSP calculation, FPGA must be initialized and set by DSP before FPGA can realize the above functions.

3 Realization of multi-phase inverter controller

The controller uses the DSP model TMS320F2812 as the main control chip. This is a chip specially designed for motor control. It not only has the characteristics of fast operation speed, but also integrates rich on-chip and peripheral resources. Using the 16 channels of 12 bit A/D integrated in the TMS320F2812, up to 16 channels of current or voltage can be sampled; the event manager module of the TMS320F2812 has a QEP circuit, which can decode and encode the orthogonal encoding pulses of the encoder. Count to calculate the rotor position and speed of the motor.

Taking into account the large resources required by the multi-phase system and the expansion of functions, the FPGA chip EP2C35F484 of Altera's Cyclone II series is used as the control chip, and the 100 MHz active crystal oscillator is externally extended as the clock input to improve the control accuracy. While completing the generation of PWM signals, FPGA also takes into account the task of fault protection. When an external fault signal of a certain phase is received, the PWM signal of this phase is blocked. Real-time hardware protection improves the reliability of the controller.

3.1 Design of communication interface between DSP and FPGA

In order to ensure the fast communication between DSP and FPGA, DSP uses external interface (XINTF) module to connect with FPGA user I/O port. Because the interface voltage of both chips is 3.3 V, the 16-bit data bus and 19-bit address bus of the DSP external interface (XINTF) module are directly connected to the write signal line XWE and the user I/O port of the FPGA to achieve parallelism. Communication.

3.2 Software design process

The system software part is mainly composed of main program and interrupt service program. The main program includes the beginning of DSP interrupt, peripherals and FPGA modulation strategy initialization; The interrupt service program mainly completes the constant voltage frequency ratio control algorithm, the speed closed-loop PID regulator control algorithm, and refreshes the frequency register.

This paper presents a method for implementing multi-phase PWM signals based on DSP and FPGA, and designs and implements a multi-phase inverter controller. This controller can perform variable frequency control and selection of multiple control methods on motors with multiple phases. Although it is not yet perfect (such as vector control cannot be achieved), its versatility and flexibility provide a multiphase motor research A good experimental platform.