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Design of eight-channel ultrasonic flaw detection system based on FPGA

Date: Jul 11, 2020

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In this paper, a design scheme of an eight-channel ultrasonic flaw detection system based on FPGA is proposed. The system uses low-power variable gain op amp and eight-channel ADC to form a highly integrated front-end amplification and data acquisition module; FPGA and ARM are used as the core of digital signal processing and the channel of human-computer interaction. In order to meet the real-time and high-speed requirements of the flaw detection system, we have adopted key technologies such as hardware alarm and peak echo envelope defect storage. In addition, the system has been significantly improved in terms of miniaturization and digitization, laying the foundation for the design of portable multi-channel ultrasonic testing systems.

Ultrasonic flaw detection is an important non-destructive testing method. It has been widely used in various industrial sectors such as large boilers, generator sets, railway bridges and aerospace, and has become an important means to ensure project quality and equipment safety.

At present, most of the ultrasonic flaw detection instruments developed in China are portable single channels. These instruments are light in weight and easy to use, which is convenient for flaw detection personnel to carry. However, single-channel instruments also have defects such as small scanning area, slow speed, and high false positive rate, which is not conducive to scanning large devices. A few multi-channel instruments are based on PCs. These instruments can quickly scan various devices, but they also have the disadvantages of large size and high price, which are not conducive to the application and popularization of multi-channel flaw detectors.

In response to some of the problems mentioned above, combined with modern digital signal processing technology and microelectronics technology, a portable eight-channel ultrasonic flaw detection system based on embedded system and FPGA is proposed. The solution uses an ARM9 processor as the main control chip, and uses a large-capacity FPGA for parallel processing, which can meet the two major requirements of portability and real-time. And through the Ethernet interface, the data can be quickly transmitted to the PC for further processing of the signal.

1 Eight channel ultrasonic flaw detection system hardware design

The system mainly includes four parts: front-end transmitter and receiver circuit, eight-channel analog-to-digital conversion circuit, FPGA data processing and logic control system and ARM post-processing module.

The main function of the front-end transmitter and receiver circuit is to generate high-voltage pulses used to excite the probe array element to generate ultrasonic waves, receive echoes, and realize the numerical control gain of the echo signals. The ADC converts the sampled analog signal into a digital signal. The FPGA module mainly implements FIR filtering of data, non-uniform compression, hardware alarm, storage of peak envelope, and related control logic. The ARM post-processing module mainly implements functions such as waveform display, channel switching, spectrum analysis, parameter presetting, human-computer interaction, and some related peripheral drivers.

1.1 Front-end transmit and receive circuit

The front-end transmitter and receiver circuit is the key to achieve the main performance indicators of the eight-channel ultrasound equipment. Generally, it consists of probe trigger circuit, isolation network, band-pass filter, and variable gain amplifier (VGA).

The variable gain amplifier part consists of three stages of variable gain AD8331 cascade. The AD8331 is a single-channel, ultra-low noise, linear dB variable gain amplifier (VGA) optimized for ultrasound system applications and can be used as a low-noise variable gain component. The device contains an ultra-low noise preamplifier (LNA), a VGA with a 48 dB gain range, and an optional gain postamplifier with adjustable output limiting. After three levels of cascading and debugging, it can achieve a gain dynamic range of 0 to 120 dB.

1.2 Eight-channel digital-to-analog conversion circuit

This system uses AD9212 as an eight-channel analog-to-digital converter. AD9212 is an eight-channel, 10-bit sampling precision analog-to-digital converter introduced by Analog Devices. The device has built-in sample-and-hold circuit, low cost, low power consumption, small size, single-chip integrated eight-channel AD circuit, which can greatly reduce the workload of circuit design and the required circuit board area. At the same time, AD9212 uses serial LVDS data output and DDR operation, which not only has a higher data output rate, but also reduces the required interface IO resources.

1.3 Data processing and logic control module

In this system, the data processing and logic control subsystem undertakes the task of processing eight channels of data in real time, configuring the parameters of the eight channels, and operating the bus to communicate with ARM. FPGA has abundant programmable resources, high integration, flexible implementation, and can well meet the design requirements.

Figure 2 Block diagram of data processing and logic control module.png

The block diagram of the data processing and logic control subsystem is shown in Figure 1. The subsystem is mainly divided into a data processing section and a logic control section. The data processing module processes the data stream transmitted by the digital-to-analog converter in real time, and the logic control module is responsible for controlling the timing of peripherals and various modules inside the FPGA. The data processing module includes DDR2 serial-to-parallel conversion, which serially converts the DDR data transmitted by the AD converter into parallel data. The parallel data passes through the FIR filter to remove the noise introduced by the analog front end, and finally the envelope data is obtained after detection and non-uniform compression. The logic control module mainly realizes the positive and negative delay control of the transmission, the gain control, and the status monitoring and control of the subsystem.

1.4 ARM post-processing system

The hardware structure of the ARM post-processing system is shown in Figure 3. ARM's high-performance processing power and strong memory management technology can effectively complete the post-processing of data, and intuitively present multiple detection modes of detection results. At the same time, it also has a wealth of on-chip peripheral device interfaces, such as network port, serial port, USB interface, which is very suitable for the application of portable embedded systems, greatly simplifying the hardware design difficulty.

Figure 3 ARM post-processing system.png

2 Eight channel ultrasonic flaw detection system software design

The application program of this system is based on Qt/Embedded development, and adopts the idea of layering and modularization in software design. Using the signal and slot mechanism in Qt, and the C++ object-oriented method, the software is mainly divided into the following modules: data communication module (drive interface), operation processing module, interface module, main control module, parameter preset module, data management module, etc. . The module can communicate with the slot through signals. 

3 Key technologies in the design of eight-channel flaw detection system

3.1 Hardware alarm technology

In the past, single-channel instruments mostly used software alarm technology. The so-called software alarm is to use the software method to compare and alarm the waveform gate. The biggest advantage is that the setting of the gate is more flexible. The disadvantage is that the alarm will lag, and the alarm response is slow. Generally speaking, under the condition of single channel and low repetition frequency, the response speed of the processor is acceptable; however, for the case of high repetition frequency and multi-channel, the software alarm will occupy a large amount of processor time, causing the alarm to lag and fail to meet the actual flaw detection requirements. Therefore, in the eight-channel instrument to be developed, only FPGA can be used to realize eight-channel real-time alarm.

Hardware alarms are mainly divided into two types: incoming wave (A door) alarm and lost wave (B door) alarm. When the peak value of the defect echo exceeds A, it triggers the incoming wave alarm, indicating that there is a large defect in the workpiece. When the peak value of the echo signal moves out of the door B, a loss-of-wave alarm is triggered, indicating that the echo signal is weak and the instrument works abnormally. This article uses FPGA to implement two kinds of alarms in FPGA. 

3.2 Storage technology of peak envelope of defect echo

The peak envelope refers to the envelope formed by the peak value of the defect echo within a certain period of time. The peak envelope is used to estimate the condition of the defect. Recording the peak envelope allows the flaw detector to make a detailed and accurate calculation of the defect size. In view of the fact that the eight-channel ultrasonic flaw detection system has many channels and a large amount of data, FPGA is used to record and store the peak envelope in real time.

The specific work flow is as follows: in the alarm state, the stored values of the echo signal memory and the alarm data memory at the same address are taken out and compared, if the former is greater than the latter, the data of the echo signal memory is written to the corresponding address of the alarm data memory At this point, refresh the old data with the new data. Otherwise, keep the original stored value unchanged. In this reciprocating cycle, the echo signal of each new frame is compared with the peak envelope stored in the alarm data memory, and the peak envelope of all defect echoes during the entire alarm period can be obtained until the end of the alarm.

3.3 Eight-channel real-time data transmission

In this system, FPGA simultaneously processes eight-channel waveform data and transfers the real-time data of the channel to be displayed into the FIFO. The ARM system needs to read in the waveform data from the FIFO and display the waveform in real time, which requires very high real-time performance for the system. In order to deliver real-time data to the application in a timely and efficient manner, we use the asynchronous notification mechanism of Linux, which combines the signal mechanism of the application layer and the interruption mechanism of the driver layer, thereby achieving the asynchronous operation of the device by the application layer.

Taking the repetition frequency of 50 Hz as an example, the FPGA sends an interrupt signal to the ARM every 20 ms. After the ARM module receives the interrupt, it reads the FIFO data in the interrupt handler and sends the SIGIO signal to the application. After the application receives the signal, it generates a Qt event and hangs it into the Qt event queue to wait for a response. The actual operation shows that the system can stably transmit and display the waveform in real time, and this scheme is feasible.

4 Experimental results

In the ultrasonic flaw detection process, by comparing the peak value of the waveform with a specific standard curve, the user can determine whether there are defects in the material and the size and location of the defect. Commonly used curves include AVG curve and DAC curve. In the case of straight probes, AVG curves are usually used. The AVG curve is generally measured by the device itself. For different apertures, different aperture curves can be obtained by measurement.

5 Conclusion

This paper proposes a design scheme of an embedded eight-channel ultrasonic flaw detector system. On the one hand, the system completely adopts digital design, utilizes the rich resources of FPGA, improves the system's ability to process parallel data, and completes the realization of the system's core functions. On the other hand, the embedded ARM post-processing subsystem greatly enhances the integration of hardware with its rich external interfaces. At the same time, the Linux operating system and QT/Embedded integrated development environment facilitate future maintenance, update and upgrade of the software system. System operation and test show that the scheme is practical and feasible, can meet the requirements of the eight-channel flaw detection system, and has broad application prospects.


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