Design of Color Screen Controller Based on FPGA

Touch screen technology is convenient for people to use and operate computers. It is a promising interactive input technology, which has been widely valued by various countries and has invested a lot of manpower and material resources to develop it, making new touch screens continue to emerge. In particular, the four-wire resistive touch screen has the characteristics of simple manufacturing process, low cost and convenient use, and has been widely used in different electronic devices.

With the rapid development of embedded technology, especially the emergence of CPLD/FPGA, the use of its IP core based on SoPC technology has brought a lot of convenience to developers. But there is no IP core of color touch screen in SoPC, so you need to write the timing control of the hardware yourself. This paper proposes a design scheme of a color touch screen controller based on FPGA. The drive logic of the color touch screen can be realized through a single FPGA chip, thereby realizing the timing control on the hardware. Based on this controller, the IP core of the color touch screen can be further developed .

1 Design of color touch screen controller

1.1 Overall structure and working principle

The controller of the color touch screen is mainly composed of TFT-LCD controller and ADS7843 chip controller. As can be seen from Figure 1, the function of the TFT-LCD controller is to buffer the image data through SDRAM, and then output the image data to the TFT-LCD. Its main functions are to complete the collection and buffering of image data, the timing control of TFT-LCD and the display of final data on TFT-LCD.

1.2 Design of TFT-LCD controller

After the image data is collected and buffered, the data can be output according to the timing diagram shown in FIG. 2 through the timing control of the TFT-LCD. The resolution of the TFT-LCD used in this design is 480×272, and its RGB data bits are all 8 bits, which can display 16 777 216 colors. Among them, PCLK is the LCD pixel clock signal, HSYNC is the line synchronization signal, VSYNC is the frame synchronization signal, VDEN is the data enable signal, VD[23:0] is the LCD pixel data output port, tvpw, tvp, tvbp, tvfp are Vertical sync pulse, vertical scan time, vertical back regression, vertical front regression, thpw, thp, thbp, thfp are horizontal sync pulse, horizontal scan time, horizontal back regression, horizontal front regression respectively.

In horizontal scanning, the display of pixels is controlled by PCLK, and a PCLK cycle determines the display of a pixel. Driven by the high level of HSYNC, PCLK will generate 480 clock cycles, so that the pixels of the image will be output point by point from left to right on the screen, completing the display of 480 pixels in a row.

2 Experimental results

2.1 Simulation verification

The entire controller is designed and simulated in Quartus II 8.0. The simulation is divided into two parts, including the timing waveform of the TFT-LCD controller and the timing waveform of the ADS7843 chip controller. The simulation results are shown in Figure 4 and Figure 5, respectively.

2.2 Final display effect

FPGA uses EP2C70F896C6 from Altera; color LCD touch screen uses WXCAT43-TG3#001R from Taiwan Donghua Company. The final display effect is shown in Figure 6.

The use of Verilog HDL to write a touch interface is too complicated. The design of the touch screen operation interface through software requires the preparation of the IP core of the color touch screen. The color touch screen controller based on FPGA designed in this design can realize the TFT- with a color depth of 24 bit and a resolution of 480×272. The LCD control and the timing control of the ADS7843 chip laid the foundation for the subsequent IP core writing.