Design of area array CCD imaging system based on FPGA

One cycle of CCD includes photosensitive stage and transfer stage. In the light-sensing stage, a clock signal is provided to the substrate. During the high signal period, the CCD is in the bias stage and starts to collect charge. The amount of stored charge depends on the external light brightness and exposure time.

A new CCD imaging system was designed using SONY inter-row transfer type area array CCD ICX415AL as the image sensor. The FPGA chip EP1C12F256 of Altera Corporation is used as the timing generator to generate the CCD driving signal. The correlated double sampling technique is used to filter out the correlated noise in the video signal and improve the signal-to-noise ratio. In the QuartusⅡ9.1 development environment, VHDL programming is used, and Modelsim SE 6.5 simulation software is used to test the truth. The experimental results show that the designed timing meets the ICX415AL timing requirements. With a 29.5 MHz clock drive, it outputs 50 frames per second, which can meet high-speed tracking requirements.

CCD (Charge Coupled Device) is a new type of semiconductor integrated optoelectronic device developed in the early 1970s. It can convert the visible light signal of the scene projected onto it by the optical lens into a proportional charge packet and drive it with a proper clock pulse. Under the directional transfer, the output becomes a voltage video image. CCD has the advantages of high integration, small power consumption, small size, low working voltage, high sensitivity, etc. It has been widely used in space remote sensing, earth observation and other fields.

According to the structure, CCD can be divided into linear array CCD and area array CCD, and area array CCD can be divided into full frame CCD (Full Frame) CCD, frame transfer (Frame Transfer) CCD and interline transfer (Interline Transfer) )CCD. The three types of CCDs have their own advantages and disadvantages. Among them, the line-shifting CCD does not require a mechanical shutter. It is the fastest and most suitable for observing fast-moving objects. In this paper, a high-speed driving circuit for line-to-line transfer area array CCD is designed.

1 Structure and working mode of inter-row transfer type area array CCD

This design uses the ICX415AL type CCD chip of SONY company. ICX415AL is a line transfer type area array CCD, the diagonal is 8 mm, the size is 8.3 μmx8.3 μm, and the total image element is 823(H)×592(V ), the effective pixel is 782(H)x582(V). It not only has the characteristics of high sensitivity and low dark current, but also has excellent anti-flowering technology. ICX415AL also has a continuously variable electronic shutter function, you can obtain images without exposure by controlling the exposure time.

The structure of ICX415AL is shown in Figure 1. Among them, the photosensitive units are arranged adjacent to the storage unit, and a number of linear CCDs with a single side transfer are arranged in the vertical direction. After the integration time is over, the photosensitive unit charge is transferred to the adjacent storage unit, and the vertical transfer pulses V1, V2 , V3 transfers to the horizontal shift register line by line under the combined action, and is read out by the amplifier under the combined action of the horizontal transfer pulses H1, H2 and the reset pulse RG.

2 Design of driving circuit for transferring line array CCD between lines

The entire circuit design is shown in Figure 2, which mainly includes bias circuit, timing drive circuit, video signal processing unit and so on. The following sections introduce these parts.

The ICX415AL bias circuit design includes power supply voltage and various driving timing voltages. After careful analysis, the vertical transfer signal voltage of the CCD is -7.5 V, 0 V, 15 V three levels, the horizontal shift signal and reset signal voltage are 5 V, the base signal voltage is 22.5 V, and the FPGA power supply voltage is 3.3 V. Comprehensive CCD power supply system requirements, select 24 V as the external voltage, use the YD12-24S15 chip to obtain 15 V and -12 V voltage, and use the YDl-24-24S05 chip to obtain 5 V voltage. The voltages of -12 V and 5 V are converted to -7.5 V and 3.3 V by the chip LM2991 and chip LT1764EQ respectively, so that the voltage required by the entire circuit is obtained.

The design of the timing drive circuit is more complicated and is crucial to the imaging effect. Therefore, the design of the timing drive circuit is the key to the entire system. The ICX415AL chip has three driving modes: progressive scan mode, field readout mode and center scan mode. The progressive scan mode has a higher resolution, and it can reach 50 frames per second under the clock drive of 29.5 MHz, which meets the needs of the design. Therefore, this design uses the progressive scan mode. In this mode, the CCD requires 7 drive signals, vertical transfer clocks V1, V2, V3, horizontal transfer clocks H1 and H2, reset clock signal RG, and substrate clock SUB that controls the exposure time. One cycle of CCD includes photosensitive stage and transfer stage. In the light-sensing phase, a clock signal is provided to the substrate. During the high signal period, the CCD is in the bias phase and starts to collect charge. The amount of stored charge depends on the external light brightness and exposure time. When a three-phase level signal as shown in FIG. 3 appears in the vertical transfer clocks V1, V2, and V3, the photosensitive phase ends, and the imaging unit charge is transferred to the adjacent storage unit in the form of a charge packet. The transfer phase is divided into vertical transfer and horizontal transfer. The vertical transfer consists of 625 cycles, each cycle, the charge moves one line in the vertical direction, the last line moves into the horizontal register, and then completes 944 cycles under the action of the horizontal shift clocks H1, H2 and the reset clock RG, one output per cycle Pixel information. The reset clock RG is used to clear the charge of the floating diffusion node, so that the next point packet can be accurately measured.

3 Waveform simulation results

This design uses Altera's Cyclone series EP1C12F25617 chip, in the Quartus II 9.1 integrated development environment, using VHDL language for programming, using Modelsim SE 6.5 simulation tool for simulation, as shown in Figure 5, the timing meets the chip manual requirements.

4 Experimental results

Download the program written in VHDL language to the FPGA, use the oscilloscope to detect the waveform is correct, connect the CCD chip, and the image signal is collected by the LVDS acquisition card and displayed on the computer, as shown in Figure 6, as can be seen from the figure, the CCD imaging system has good imaging effect and meets the design requirements.

In conclusion

Based on the analysis of the driving sequence of the SONY ICX415AL inter-row transfer area array CCD, the design scheme of the driving timing generator based on FPGA is proposed, and the design scheme is implemented using VHDL language. The whole design fully combines the advantages of simple design, flexible debugging and superior performance of FPGA devices and the hardware description ability of VHDL language, which is easy to learn and understand. The CCD camera has a frame rate of 50 frames per second, and is suitable for observing high-speed moving objects. The imaging effect is good, and it has been used in actual projects.