Design and Implementation of Reconfigurable Signal Source Based on SOPC and DDS IP Core

SOPC (System on a Programmable Chip) is a flexible and efficient SOC solution proposed by Altera. It integrates the functional modules required by system design such as processor, memory, I/O interface, LVDS, CDR into a programmable logic device to build a programmable system on chip. It has a flexible design method, the software and hardware can be cut, expanded, and upgraded, and has the function of software and hardware programmable in the system. SOPC's core device FPGA has developed into a practical technology that allows system designers to minimize the time and risk of developing new products. Most importantly, FPGAs with field programmability extend the product's time in the market, thereby reducing the threat of being eliminated by a new generation of similar products. This article takes the all-digital frequency synthesis technology-direct digital frequency synthesis technology (DDS) as the theoretical basis, using advanced on-chip programmable technology to implement the DDS IP core function on an FPGA chip, and the DDS IP core and Nios II processing The device core and other peripherals are packaged together to make a system on chip, which greatly simplifies the design difficulty of the circuit.

1 Basic principles of DDS

The phase accumulator includes an adder and a phase register. Each time a clock pulse comes, the adder adds the frequency control word to the data in the phase register. The phase register can feed the new phase data generated by the adder after the previous clock to the input of the adder, so that the adder continues to add the phase data and the frequency control word under the action of the next clock. In this way, the phase accumulator performs linear phase accumulation under the action of the reference clock. When the phase accumulator reaches the upper limit, an overflow occurs and a periodic action is completed. This period is a cycle of the synthesized signal, and the overflow frequency of the accumulator is the synthesized signal frequency of the DDS. The phase control word is used to set the phase value of the initial phase of the phase accumulator. The phase accumulator does not participate in the addition operation during its operation.

Under the control of the reference clock, the phase accumulator is controlled by the frequency control word to output phase data, and the phase data output from the phase accumulator is used as the address of the phase/amplitude variable conversion circuit to search it. The phase/amplitude conversion circuit maps the phase information of the phase accumulator to digital amplitude information, and then passes the digital amplitude data through the D/A converter to obtain the corresponding staircase wave, and finally smoothes the staircase wave through the low-pass filter. Obtain a continuously changing output waveform determined by the frequency control word.

2 Design of DDS IP core

According to the basic theory of DDS, the DDS IP core is divided into a phase accumulation module, a DDS control module, a waveform selection module, and a waveform LPM_ROM module.

2.1 Design of the phase accumulator module

The phase accumulator is the key to the DDS IP core design. It determines the frequency range and resolution. The 32-bit binary accumulator used in this design takes the high ten bits of the accumulator as the address of the look-up table (phase-amplitude conversion circuit). value. In order to improve the speed of the system, 7-stage pipeline technology is used in the design of the accumulator. The key code of the first-stage pipeline implementation described in Verilog HDL is as follows:

Similarly, the design of the remaining pipelines can be completed.