Design and implementation of digital photo frame based on FPGA and IP core

This system uses the economical Cyclone II FPGA chip as the core, based on the Nios II soft core processor, which is designed and implemented by a combination of software and hardware.

As a combination of digital consumer goods and decorations, digital photo frames are receiving more and more attention in the market. The current digital photo frame solutions mostly use the MCU as the core architecture, and the photo frame functions are fixed, which is not convenient for product upgrades. In response to the above problems, this article designed a multi-function digital photo frame based on Nios II, the album mainly contains the following functions: support for image display of many common file formats including BMP, JPEG; image rotation, zoom, browse switching and other special effects; Support background music playback during picture browsing; image data can be updated through SD card with FAT file system, and it also has extended functions such as time display. In the system, complex operations that require a lot of time (such as image decoding, various special effect functions of the image, and SD card control) will be implemented with custom modules mounted on the Avalon bus. The processing time is shortened and the system response speed is improved. The system uses SoPC technology based on Nios II processor, which makes the digital photo frame have the advantages of high flexibility, reconfiguration, and easy upgrade.

1 Overall design

This system uses the economical Cyclone II FPGA chip as the core, based on the Nios II soft core processor, which is designed and implemented by a combination of software and hardware.

The SD card is used as a file storage medium for storing audio and image files, and the SD card controller is written to read and write control of the SD card; the LCM display screen is used as the display interface of the digital photo frame, and the SRAM is used as the LCM display cache to store image data for LCM refreshes, and the image display is controlled by the LCM_SRAM IP core; SDRAM is the Nios II soft core program running space; EPCS configures the FPGA; Flash is used to store software code and data.

2 Function module design

According to the functions to be realized by the digital photo frame, the following modules are designed:

2.1 LCM_SRAM IP core design

The main functions of this module are image data storage, LCM parameter configuration, image scaling, rotation, and switching effect control. Realize the image switching effect in hardware, improve real-time performance and reduce the dependence on CPU.

2.1.1 Realization of switching special effects

In the design, by controlling the LCM to read the address of the SRAM to achieve different image switching effects, such as the upper cut-in, lower cut-in, blinds, diamonds and other eight modes appear cyclically. When switching, the data of the old and new images exist on the LCM. Therefore, the data of the two images needs to be stored in the cache. Taking the louver effect as an example, each line is divided into 20 strip-shaped areas by dividing each line of the LCM by 16 pixels.

The above is about the design and implementation of digital photo frame based on FPGA and IP core. I hope it will help you.