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Cross Clock Domain Handling - Sub-stable and Synchronizer

Date: Jul 12, 2021

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The design of digital circuits usually requires special handling when it comes to cross-clock domain (CDC) circuits, such as synchronizers, asynchronous FIFOs, and so on. So why CDC needs special treatment, and what problems will result if it is not done.


Sub-stable

We all know that there are two most important concepts in digital circuits, build time and hold time. By meeting the setup time and hold time, we can ensure that the signal is sampled correctly, i.e., a 1 is a 1 and a 0 is a 0. However, if the setup time and hold time are not met, the signal will enter an unstable state where it is impossible to determine whether it is a 1 or a 0, which we call sub-stable. This sub-stable signal will be in a period of time in the oscillating state, until stable, and the stable state value and the sampled value is irrelevant, may be 0 or 1.

Cross Clock Domain Handling.png

The figure shows the case of a failed asynchronous clock sample. When the change in data (adat) is close to the change edge of the sampled clock (bclk), it causes the sampled signal (bdat1) to enter a sub-stable state because the build-up time is not satisfied.


Asynchronous clocks are often difficult to avoid in the case of Figure 1 due to the different clock phases, which is the reason why sub-stability is prone to occur when crossing the clock domain.


What problems can be caused by sub-stability

Since a sub-stable signal will be in an oscillating state for a period of time, subsequent different logic may recognize the signal as a different state value, or even subsequent logic may also appear sub-stable, leading to errors and confusion in the logic, such as incorrect jumps in the state machine and thus locking up in a certain state.


Synchronizers

The most commonly used synchronizer is a two-stage flip-flop, as shown in the figure.

Cross Clock Domain Handling2.png

The first-stage flip-flop samples a sub-stable state, and the second-stage flip-flop samples a steady-state signal after a clock cycle of waiting, for the purpose of eliminating the indeterminate state. However, note that such a synchronizer only reduces the probability of sub-stable occurrence, and does not completely eliminate the occurrence of sub-stable states. The smaller the MTBF value, the higher the frequency of sub-stability.

Cross Clock Domain Handling3.png

The figure indicates the influence factor of MTBF, and it can be seen that the higher the clock frequency, the higher the frequency of data change, and the smaller the MTBF, i.e., the higher the frequency of sub-stability occurrence.


For some high-frequency circuit designs, the MTBF of the synchronizer composed of two-stage flip-flops is still very small, and it is time to consider adding another level of flip-flops, i.e., using three-stage flip-flops. In addition, we also hope that when the data is sampled by the asynchronous clock data change frequency is also as small as possible, so the general data in the cross-clock domain before the best can be used to register a beat to reduce the variation of data, thereby reducing the probability of sub-stable occurrence.


It is worth noting that the use of synchronizers only eliminates the uncertainty, but the output of the synchronizer may still be wrong, the sampled signal may be 1, but the synchronizer output is indeed 0. Whether such an error is acceptable to the circuit depends on the design, which brings us to another topic, how to make the system insensitive to the errors generated, which will not be discussed in this paper.


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