Changes in programmable logic device CPLD: from PAL to PLD

PAL is followed by PLD. PLD and PAL devices are very similar, but add some other features to become a truly programmable device, and more practical. The main difference between this device and the simple PAL device is that it contains fully programmable macrocells and variable product term allocation.

The macrocell provides multiple programmable options to achieve product and output. Programmable macrocells can also be fed back to the array or use output pins as input. The flexible PLD macrocell becomes a truly practical device for implementing logic functions. The first PLD is shown in Figure 1.6.

CPLD was further developed when the concept of PLD was further expanded. Similar to a PLD composed of multiple PALs and macrocells, CPLD contains multiple PLD logic modules connected to I/O pins, which are connected to each other through a programmable interconnect architecture. This measure can increase the amount of logic in a device.

The logic module in CPLD is usually called a logic array module (LAB), and each LAB is like a PLD. CPLD LAB generally contains 4 to 20 macrocells. The programmable arrays in LAB are very similar to PAL or PLD arrays.

However, the assignment of variable product terms in CPLD and PLD is different. Macrocells in CPLD LAB usually include additional AND gate logic, which is fed directly back to the array. This additional logic can be used to form additional product terms, called extension terms. The extra product term generated by the expansion logic can be used in the current macrocell to expand the logic function.

Other macro units can also share and use extension items. In this way, for a macro cell that requires a product term, the product term can be established only once, rather than every time. This is a more efficient way to reduce logic waste.

Note: The disadvantage of using extended term logic is the additional delay caused by the extended product term, and the delay using extended term logic is known. Therefore, this should be considered when placing logic and performing timing analysis.

Except for LAB, other structures in CPLD are similar to PAL and PLD, but the configuration is more advanced. The interconnections between LABs are called programmable interconnect arrays, or PI or PIA. PI is similar to the programmable arrays in PAL and PLD, using the same programming techniques. PI provides all the traces required for data transfer between LAB and between LAB and I/O pins.

Through PI, the input and output of any LAB can be connected to any other LAB or I/O. This is the key to achieving very flexible programmable devices. Another improvement of CPLD over PLD is the addition of a separate I/O control module. In PLD, the I/O pins are directly connected to the logic. In CPLD, PI separates the I/O pins from the main logic of the device. I/O pins have their own control logic to achieve a variety of features. Any pin has multiple I/O standards, input, output, or bidirectional operation. It does not need to force certain pins to be used as inputs.

The biggest advantage of CPLD over PLD lies in the number of logic and wiring options. LAB logic and PI are fully programmable and have great design flexibility in monolithic devices. CPLD's I/O features and functions far exceed the simple I/O of PLD, and provide more options and control functions on how I/O works.

Like PAL and PLD, CPLD can be connected to work instantly when it is powered on the circuit board. They have a very low cost and take up very little circuit board area. The non-volatile EEPROM programming architecture makes it very suitable for in-system programming methods for testing and debugging, without reprogramming it when the circuit board is powered up. Current Altera CPLDs include MAX 3000 and 7000 series devices, as well as MAX II and MAX IIZ series.