Date: Jul 07, 2020
Click Count: 2720
Single pulse generators are commonly used in FPGA development. Some articles have introduced circuits that generate single pulses. The pulse width and phase of the generated single pulses cannot be synchronized with the clock, and can only be used in occasions where the requirements are not strict. The subject I am currently working on requires a keyed single pulse generator with the same width as the clock cycle and the same phase as the clock cycle. The keyed single pulse generator requires a key to generate a single pulse, but most development boards with FPGA chips provide high-frequency clock pulses, and there will be jitter problems when pressing the keys. To this end, the author specially designed a key debounce circuit to eliminate jitter and provide a stable key signal for generating a single pulse.
1 Principle of key debounce circuit
In order to make the key debounce circuit module simple and transplantable, the key debounce function is implemented in the form of a counter.
The counter modulus n is determined according to the pulse width of the jitter signal and the period size of the sampling pulse signal CLK. Counting modulus n = delay/pulse signal sampling period. Generally, the key jitter time is 5 to 10 ms, or even longer. The system clock provided by the author's development board is 24 MHz, calculated according to the formula, when the counter modulus value takes 20 bits, when the count reaches 219, that is, h8 0000, the delay is about 22 ms. During the counting period, it is considered to be the jitter signal of the key, and no sampling is done; the counter stops counting, and the sampling signal is considered to be a stable key signal. In this way, the jitter signal with the key time less than 22 ms can be filtered.
Introduce a sampling pulse signal CLK, and input the key signal KEY. When the KEY input is low, the counter starts to count up. When the count reaches h8 0000, the highest bit Q19 in the counter is 1, the counter stops counting, and the output Q19 is used as the stable output of the key. During the counting period, Q19 output is 0; KEY input high power The counter is cleared and the Q19 output is 0. So the circuit needs 22 ms to get a valid signal.
2 Principle of key-controlled single pulse generator circuit
The key-controlled single pulse generator uses the above-mentioned circuit to solve the key debounce problem and obtain a stable signal. Use two D flip-flops and an AND gate to generate a single pulse, as shown in Figure 1.
The D flip-flop U2A is triggered after receiving the stable signal D1=1. The Q1 terminal in the flip-flop U2A gets a positive pulse synchronized with CLK. Output Q1 to D flip-flop U3A, get a positive pulse delayed by one clock cycle than Q1, and invert the output of Q2 to get a negative pulse. The outputs of Q1 and Qn2 as an input of an AND gate will output a single pulse with a pulse width twice that of the original clock cycle.
In order to make the pulse width of the single pulse equal to the clock period and the same phase as the clock period, the circuit design in Figure 1 is improved, as shown in Figure 2.
In Figure 2, a NOT gate is added before the clock is sent to the D flip-flop, so that the Q1 terminal generates a positive pulse synchronized with nCLK (CLK's reverse pulse signal), the AND gate outputs a single pulse and CLK is half a clock cycle difference, as D The input D4 of the flip-flop U4A is triggered at the rising edge of CLK U4A, so that the pulse width of the single pulse is the same as the clock cycle, and the equal pulse width is realized. And delayed by half a clock cycle to make the output pulse correspond to the clock cycle, to achieve phase adjustment. The timing diagram of the entire single pulse generator is shown in Figure 3 (t1 and t2 in Figure 3 are the moments when any key is pressed and the key is raised).
3 Verilog HDL language description based on key debounce counter and single pulse generator under FPGA
The key debounce counter circuit in Fig. 1, its Verilog HDL language code to describe is as follows:
The reset n_rst and key n_Kd in the code are both active low. The Verilog HDL language code of the keyed single pulse generator is as follows:
The D flip-flop DFF is also used in the code, the code to implement this module is relatively simple
The design in this article implements a keyed single pulse generator, generates a pulse width equal to the clock pulse, and outputs a single pulse corresponding to the clock cycle, and solves the problem of key debounce. It can be applied to various FPGAs that need to generate a single pulse Circuit design. The key debounce circuit can be independently applied to other FPGA circuit designs. The 20 b counter designed in this article is based on the author's subject needs. In other designs, the counter modulus value can be calculated according to the key jitter time, and the counter can be calculated to design the counter.