Built for chips: Xilinx introduces the world's largest FPGA

Recently, Xilinx announced the launch of the world's largest FPGA chip "Virtex UltraScale+ VU19P". V is Xilinx's third-generation FPGA that has set a new world record and will widely support related applications such as test and measurement, computing, networking, aerospace and defense. It is reported that VU19P uses TSMC's 16-nanometer process, and subsequent products will use a 7-nanometer process.

Big man contains big energy

●VU19P transistor density increased by 1.6 times compared to the previous generation VU440, but power consumption was reduced by 60%. The ultra-high density of 35 billion transistors has exceeded the 32 billion transistors of AMD Xiaolong processors.

●In terms of specific parameters, VU19P is based on TSMC's 16nm process, integrating 35 billion transistors, 9 million system logic units, DDR4 memory bandwidth up to 1.5 Terabit per second, transceiver bandwidth up to f 4.5 Terabit per second and over 2,000 User I/O.

●This world's largest FPGA has a 1.6-fold increase in VU19P capacity compared to the previous generation industry's largest-capacity FPGA, while reducing system energy consumption by 60%.

● VU19P not only helps developers accelerate hardware verification, but also helps them integrate software in advance before ASIC or SoC becomes available.

●VU19P not only brings cutting-edge chip technology, but also provides reliable and proven tool flow and IP support.

●This world's largest FPGA can support the simulation and prototyping of the most advanced ASIC and SoC technology in the future. At the same time, it will also widely support related applications such as test and measurement, computing, networking, aerospace and defense.

● It can also support various complex emerging algorithms, such as artificial intelligence, machine learning, video processing, sensor fusion, etc.

The FPGA behind the chip is inseparable

The development of AI and 5G technologies puts higher and higher requirements on chip architecture and software support. The chip design is more complex, and the industry needs a larger capacity FPGA to achieve efficient simulation and functional verification.

The chip industry is a high-input, high-risk, and slow-return industry. Unlike software that can be revised and quickly iterated, the iteration cycle of the chip will be very long. If you have already streamed, correcting an error may take thousands of dollars to stream again in half a year.

On the one hand, chip manufacturers need to rely on FPGA for simulation and prototyping; on the other hand, CPU, GPU, FPGA and ASIC (application specific integrated circuit) these different processor manufacturers are increasingly competitive in the AI market.

Even when chip giants such as Xilinx and Intel design chips such as CPUs, they will first emulate on FPGA and then tape out, not to mention the AI-specific chips released by many AI algorithm companies in recent years.

With the current progress of 5G and the advancement of AI, FPGAs are expected to reach approximately US$12.521 billion in 2025. In 2013, the global FPGA market size was 4.563 billion US dollars, and by 2018 this value will increase to 6.335 billion US dollars.

In the global FPGA market, Xilinx and Altera have a combined market share of approximately 90%. Xilinx revenue of 850 million US dollars this quarter, an increase of 24% year-on-year; net profit of 241 million US dollars, an increase of 27% over the same period last year.

Coming for AI+Car+Advanced Chip

At present, all the most advanced chips on the market need to use FPGA chips for simulation and prototyping before tape-out. VU19P is born for this purpose. It is a chip built for chip manufacturers.

VU19P can not only help developers accelerate hardware verification, but also help them integrate software in advance before ASIC or SoC becomes available.

In addition to hardware technology, Xilinx also provides the VIVADO design suite, and provides tool flow and IP support for users, allowing chip manufacturers to integrate software before the chip is available, reducing costs, reducing tape-out risks, and improving Efficiency and speed up the product listing process.

Chips are getting more sophisticated and more complex. Now all the most cutting-edge chips on the market need to use FPGA chips for simulation and prototyping before tape out. Therefore, Xilinx introduced this VU19P for chip manufacturers, which can support more complex AI, 5G, automotive, and visual algorithms can also support larger ASIC/SoC design requirements.

Borrowing 5G Dongfeng FPGA revenue will blossom

With the progress of the current 5G era and the speed of AI advancement, MRFR predicts that FPGAs will reach approximately US$12.521 billion in 2025. In 2013, the global FPGA market size was 4.563 billion US dollars, and by 2018 the global FPGA market size gradually increased to 6.335 billion US dollars.

As for the global FPGA market distribution, by region, the largest is currently in the Asia-Pacific region, accounting for 39.15%, North America accounting for 33.94%, and Europe accounting for 19.42%.

By 2025, the proportion of the Asia-Pacific region will continue to increase to 43.94%. The reason for this is mainly because the major growth of the downstream application market in the future is mostly concentrated in the Asia-Pacific region.

5G will bring 1.5 times the number of base stations, 2 times the silicon content, and 1.3 times the market share, and is expected to increase Xilinx's wired and wireless business group opportunity revenue to 3 to 4 times in the 4G era.

The battles of various crafts have never stopped

No matter who took the lead in adopting the new process, its design will win and the market share will increase accordingly.

● At 28 nanometers, Xilinx beat Altera with a slight advantage. For Xilinx, this is the first time it has designed products on TSMC’s process nodes, so the first win is very important.

● By 20 nanometers, Xilinx had already opened up the advantage gap with Altera, forcing Altera to be forced to switch to Intel's 14 nanometers.

● Xilinx has made persistent efforts to lead the market again with TSMC's 16-nanometer, while Altera's 14-nanometer device has been postponed repeatedly.

● When Intel and Altera’s 14-nanometer devices finally came out, because their products were very competitive in terms of density, performance, and price, it once again ignited the war between the already defunct FPGA giants.

● Intel’s 10 nanometers are still delayed, which has made Xilinx dominate the FPGA market since Altera was acquired, except for Intel’s cloud market.

The competition between FPGA and ASIC will continue, but at 7 nanometers, the speed and density of FPGA have been greatly improved, and the power consumption is lower, so this competitive landscape may change, especially in those made by ASIC and FPGA. Evenly divided in the SoC prototype and simulation market.

Be the biggest to meet the higher level of competition

The launch of ACAP will help Xilinx to compete with higher-level opponents in a whole new market. Flexibility and adaptability are a core selling point of ACAP. Obviously, this is for Intel and Nvidia. Especially in the era of artificial intelligence, Xilinx also wants to use this advantage to achieve a higher ranking for Intel and Nvidia.

Since Altera, the biggest competitor, was already included in Intel's pockets in 2015, Xilinx's new competitors have become Intel, Nvidia and other companies.

This is equivalent to Xilinx's successful promotion, and will compete with companies like Intel and Nvidia at a higher level.

In the era of the big data explosion and post-Moore's Law, the trend of computing isomerization has accelerated. The traditional CPU has been unable to process the data generated by all walks of life. Although the GPU is better than the CPU in some aspects, it can not adapt to all situations. Therefore, more heterogeneous computing is needed now.

When facing competitors such as Intel and Nvidia, we should focus on Xilinx's core competitiveness, that is, at the hardware level, we can optimize very flexibly and adaptively according to different workloads and efforts, rather than traditional Compete with them.

To sum up

As the current chip manufacturing process becomes more sophisticated and chip design more and more complicated, the upfront cost of chip design manufacturers has soared, and the risk of tape-out has also further increased. The demand for reducing chip cost, tape-out risk, and time-to-market will be Further eruption.