Application of FPGA in software radio

Software Radio Products (SDR) is a wireless device with a reconfigurable hardware platform that can span multiple communication standards. Because of lower cost, greater flexibility and higher performance, software radio products

It has quickly become the de facto standard in the military, public safety, and commercial wireless fields. One of the main reasons why SDR has become popular is that it can perform baseband processing and digital intermediate frequency (IF) processing on a variety of waveforms. IF processing expands the field of digital signal processing from baseband to RF. The ability to support baseband and intermediate frequency processing increases system flexibility while reducing manufacturing costs.

Baseband processing

Wireless standards are constantly evolving, supporting higher data rates through advanced baseband processing technologies such as adaptive modulation coding, space-time coding (STC), beamforming, and multiple-input multiple-output (MIMO) antenna technologies. Baseband signal processing devices require huge processing bandwidth to support the computationally intensive algorithms in these technologies. For example, the United States Military Joint Tactical Wireless System (JTRS) defines more than 20 types of military wireless

Different wireless waveforms. The computing power required for some more complex waveforms is millions of instructions per second (MIPS) on a standard processor, or thousands of logic units if implemented on an FPGA.

Coprocessor features

SDR baseband processing usually requires a processor and FPGA. In such applications, the processor handles system control and configuration functions, while the FPGA implements a computationally intensive signal processing data channel and control to minimize system delay. When it is necessary to switch from one standard to another, the processor can dynamically switch between the main parts of the software, and the FPGA can be completely reconfigured as needed to achieve a specific standard data channel.

FPGA can be used as a co-processor to connect with DSP and general-purpose processor, which has higher system performance and lower system cost. Freely choosing where to implement the baseband processing algorithm provides another way of flexibility for implementing the SDR algorithm.

Baseband components also need to be flexible enough to allow the required SDR functions to support migration between enhanced versions of the same standard and to support completely different standards. Programmable logic combined with soft core processors and IP has the ability to provide remote upgrades in the field. Figure 1 is a block diagram where the FPGA can easily reconfigure the baseband transmission function that supports WCDMA/HSPDA or 802.16a standards through IP functions such as Turbo encoder, Reed-Solomon encoder, symbol interleaver, symbol mapper, and IFFT. .

Digital IF processing

Digital frequency change has higher performance than traditional analog wireless processing. FPGA provides a highly flexible and integrated platform on which to implement a large amount of digital IF function with reasonable power, which is a key factor in portable systems. IF functions that can be implemented on FPGAs include digital upconverters (DUC) and downconverters (DDC), as well as digital predistortion (DPD) and crest factor reduction (CFR), helping to reduce the cost and power of power amplifiers (see Figure 2 ) --- Note: DUC: digital upconverter; CFR: crest factor reduction; DPD: digital predistortion; DDC: digital downconverter; PA: power amplifier; LNA: low noise amplifier.

Digital upconverter

Digital format (generally required between the baseband processing unit and the upconverter) can be smoothly added to the front end of the upconverter. This technology provides a fully customized front end for the upconverter, allowing channelized high-bandwidth input data. Custom logic or soft core embedded processors can be used to control the interface between the upconverter and the baseband processing unit implemented in the FPGA. --- In digital up-conversion, the input data undergoes baseband filtering and interpolation before being orthogonally modulated with an adjustable carrier frequency. In order to implement an interpolated baseband finite impulse response (FIR) filter, there must be a trade-off between the speed area and a fixed or adaptive architecture optimized for a specific standard. The NC oscillator core can also produce a variety of architectures, they have more than 115db parasitic dynamic range and very high performance. Depending on the number of frequency assignments supported, multiple upconverters can be easily instantiated in FPGA.

Crest factor reduction

3G CDMA-based systems and multi-carrier systems such as orthogonal frequency division multiplexing (OFDM) signals have a high peak-to-average ratio (crest coefficient). Such a signal will greatly reduce the efficiency of the power amplifier in the base station. For multi-waveform standards, the crest factor reduction technology implemented in FPGAs is a cost-effective way to reduce the cost and complexity of power amplifiers.

Digital predistortion

High-speed mobile data transmission uses non-constant envelope modulation techniques such as QPSK and quadrature amplitude modulation (QAM). This has strict requirements on the linearity of the PA. DPD linearization techniques, including lookup tables and polynomial methods, can be effectively implemented in FPGAs that contain DSP blocks. The multipliers in these DSP blocks can run at a very high clock rate and can effectively implement complex multiplication by time-sharing. When FPGAs are used in SDR base stations, FPGAs can be reconfigured for specific standards to implement the appropriate DPD algorithm, effectively linearizing the PA. Digital down converter

On the receiver side, digital IF technology can sample the IF signal, perform channelization and sample rate conversion in the digital domain. Using downsampling techniques, high-frequency IF signals (at the same time above 100MHz) can be quantized. Because different standards have different chip/bit rates, non-integer sampling rates are required for SDR applications,

Convert the number of samples to an integer multiple of any standard basic chip/bit rate.

In conclusion

FPGA provides a common computing structure, very suitable for software radio products, the baseband and IF digital processing needs. In addition, FPGA, as a hardware coprocessor for general-purpose processor or DSP software processing, can enhance functions, improve throughput, reduce system cost and reduce system power.