An Interface Circuit Design Based on FPGA

In avionics systems, it is often necessary to perform bidirectional data conversion on the 1553B bus and ARINC429 bus to meet the interface requirements of different electronic devices. Because the two bus standard transmission protocols are different, the transmission rate and data format are quite different, the conventional system needs a variety of professional data conversion chips to meet the data conversion requirements. This article introduces a general data conversion module design based on FPGA.

In the field of aviation, the 1553B bus and the ARINC429 bus are two widely used bus standards. The 1553B bus is more commonly used in aircraft avionics systems, and the ARINC429 bus is more commonly used in airborne weapon systems, as the weapon system communicates with the avionics system. The transmitting device of the control agent needs to convert data between the two bus standards. The two bus data formats are now briefly introduced.

1) Introduction to GJB1553B bus

The GJB1553B data bus uses the Manchester encoding and decoding protocol to perform data transmission in an asynchronous, command/response mode, usually in half-duplex mode, and its transmission rate is 1Mbit/s. Manchester code is different from the commonly used non-return-to-zero (NRZ) code In the circuit, the "0" of the NRZ code is represented by a low level; the "0" of the Manchester code is represented by a level transition from low to high. Similarly, the "1" of the NRZ code is represented by a high level; the "1" of the Manchester code is represented by a level transition from high to low. In practical applications, differential Manchester codes are used.

2) Introduction to ARINC 429

The ARINC429 bus is one of the more widely used airborne aviation buses. It is a unidirectional and unidirectional broadcast bus. Its information transmission rate is 12.5~100kbit/s [2]. ARINC429 specifies that data transmission uses dual Polarity reset

1 FPGA-based conversion circuit hardware design

The core job of data conversion is to encode and decode data of various bus standards. In traditional data conversion circuits, professional bus code chips of various bus standards are generally used to encode and decode the data, and then process the data. The traditional conversion circuit design is relatively simple, but the power consumption is high and the resources of programmable logic Not fully utilized. Now we introduce a design of data conversion circuit based on FPGA.

Data conversion hardware circuit design

The data conversion circuit mainly includes FPGA, DSP and peripheral drive conditioning circuit. Among them, DSP controls the working sequence of each module. FPGA is responsible for Mancode encoding and decoding, DSP peripheral control logic, data format conversion, clock signal generation, and data temporary storage. The data is stored in CMOS static RAM with high speed and low power consumption.

Considering the data communication between the various modules of the circuit, the data line needs to occupy a large area of PCB space, and crosstalk may occur between high-speed signals. Therefore, here we integrate the codec part of the 1553B chip into the FPGA, and the peripheral adjusts the data level to a range suitable for FPGA reception through a mode transformer and a simple shaping circuit. This can reduce the power consumption of the entire data conversion circuit, improve the integration of the CPU control board, reduce the amount of heat, simplify the wiring of the PCB board, and improve the stability of the entire system.

System simulation verification

The entire FPGA function module is integrated with Verilog language. Using FPGA simulation tools to simulate key signals and modules in the design can greatly save development time, improve the stability of system operation, and reduce development costs.

1) GJB1533B data conversion implementation

The GJB1553B data uses Manchester encoding. To realize data conversion, the Manchester code must be decoded. The Manchester encoding and decoding logic circuit consists of a sync header identification logic circuit, a data sampling logic circuit, and a decoding logic circuit. The identification of the synchronization header is more critical. If it is not correctly identified, it may cause the command to be lost or the parameter settings to be incorrect. The technology we use here is: the data sampling logic circuit clock monitors the data input line, and the level transition on the data input line is used as a trigger event. Whether the trigger event is valid is determined by the following conditions:

If there are 1.5 low levels and two effective Manchester code bits continuously in the data queue collected later, the command word sync header is considered valid; if there are 1.5 high levels and continuous in the data queue collected later With two valid Manchester code bits, the data word sync header is considered valid. After receiving 17 consecutive Manchester codes, the last bit is the odd parity bit. If the odd parity bit is correct, it means that a correct and complete word has been received. Is the 16-bit word a command word or a data word from the sync header? The format is determined.

2) ARINC429 data conversion implementation

The basic information unit of ARINC429 data is a data word composed of 32 bits, and each data word is divided into 5 groups, namely: bits 1~8 are the flag bits (LABEL), and bits 9~10 are the source/destination identification Bit (SDI), bits 11~29 are the data area (DATA), bits 30~31 are the sign bit (SSM), and bit 32 is the parity bit (PARITY). In fact, the use of ARINC429 data bits can be largely defined by the system designer. Under the basic characteristics of 32bit serial transmission, as long as the sender and receiver use the same agreement.

Conclusion

It can be seen from the simulation that GJB 1 5 5 3 B and ARINC429 are accurately and steadily converted into binary data after being decoded by their respective codec modules inside the FPGA. Due to the strong portability of Verilog language, the codec modules can be directly transplanted to other modules Achieve two kinds of bus data communication transmission.