Five points of introduction of Xilinx FPGA development tools

Xilinx FPGAs are mainly divided into two categories. One focuses on low-cost applications with medium capacity and performance that can meet general logic design requirements, such as the Spartan series; the other focuses on high-performance applications with large capacity and performance that can meet various high-end Applications, such as the Virtex series. Each operation under Xilinx corresponds to a tool, logic synthesis, netlist, and constraint fie merging, placement and routing, and so on. Below FPGAKey will give an introduction to each Xilinx FPGA development tool, hoping to help those who want to know.

1. XST (Xilinx Synthesis Technology) is a logic language synthesis tool exited by Xilinx. What it does is to synthesize the logic expressed in HDL language into a specific netlist file, that is, NGC file. NGC contains the logic design of the circuit.

2. Ngdbuild, in Xilinx's ISE, integrated development environment, there is a step called Translate which actually corresponds to the Ngdbuild operation. Ngdbuild reads the NGC netlist file generated by XST and combines it with UCF (user constraint file) to generate an NGD file (Native Generic Database) ), this file describes the logic of the design, including various logic units, such as AND gate, NOT gate, LUT, flip-flop, and RAM. After the Ngdbuild operation is completed, a .bld report will be generated to record various information about the Ngdbuild operation.

Tip: If you want to learn about Xilinx FPGA, you might as well click to learn about it first.

3. Map. In Xilinx's ISE integrated development environment, there is also a map called map that corresponds to the Map operation. The map reads the NGD netlist file generated by Ngdbuild and then puts the logical original (NAND gate) contained in the NGD netlist file. And RAM, etc.) are mapped to the components in the FPGA. One output of Map is a .ncd file and the other is a .pcf file. After the Map operation is completed, a .mrp report will be generated to record various information in the Map process.

4. Par. The operation that Par does is place and route. The input of Par is the output file .ncd file and .pcf file of the Map operation. The output of Par is also a .ncd file. These two .ncd files have different names. After the Map operation is completed, a .par report will also be generated to record various information in the Par process. At the same time, Par will also generate PAD, CSV, and TXT files to record pin allocation information.

5. Bitgen, Bitgen is the operation of generating configuration streams. The input of Bitgen is the output file .ncd file of the par operation. If the output of Bit is not specified, the default is the routed.bit file. Also after the Bitgen operation is completed, one will be generated. The bgn file is used to record various information in the Bitgen process.

The above is a five-point introduction about Xilinx FPGA development tools. If there is any omission, please add it or post a topic directly on the FPGAKey forum for exchange For more FPGA content, please pay attention to the FPGA Technology of FPGAKey.