This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Technology > FPGA > Application of Xilinx ZYNQ FPGA development board in artificial intelligence image processing - FPGA Technology

Application of Xilinx ZYNQ FPGA development board in artificial intelligence image processing

Date: Dec 29, 2020

Click Count: 261

PYNQ-Z2 is a platform based on Xilinx ZYNQ-7000 FPGA. In addition to inheriting the powerful processing performance of the traditional ZYNQ platform, it is also compatible with the Arduino interface and the standard Raspberry Pi interface. This makes the PYNQ-Z2 extremely scalable and Open source. PYNQ is a new open-source framework that enables embedded programmers to give full play to the functions of Xilinx Zynq All Programmable SoC (APSoC) without designing programmable logic circuits. Different from the conventional method, through PYNQ-Z2, users can use Python to program APSoC, and the code can be developed and tested directly on PYNQ2. Through PYNQ-Z2, the programmable logic circuit will be imported as a hardware library and programmed through its API in basically the same way as importing and programming a software library.

PYNQ-Z2.jpg

Xilinx ZYNQ FPGA development board: PYNQ-Z2

ZYNQ XC7Z020-1CLG400C:

  • 650MHz dual-core Cortex-A9 processor

  • DDR3 memory controller with 8 DMA channels and 4 high-performance AXI3 slave ports

  • High bandwidth peripheral controller: 1G Ethernet, USB 2.0, SDIO

  • Low bandwidth peripheral controller: SPI, UART, CAN, I2C

  • Programmable from JTAG, Quad-SPI flash memory, and microSD card

  • Artix-7 series programmable logic

  • 13,300 logic slices, each with four 6-input LUTs and 8 flip-flops

  • 630 KB of fast block RAM

  • 4 clock management slices, each slice has a phase-locked loop (PLL) and mixed-mode clock manager (MMCM)

  • 220 DSP slice

  • On-chip analog-to-digital converter (XADC)

Storage:

  • 512MB DDR3 with 16-bit bus @1050Mbps

  • 16MB Quad-SPI flash memory with factory programmed global

  • Unique identifier (compatible with 48-bit EUI-48/64™).

  • MicroSD slot

powered by:

  • Powered by USB or any 7V-15V power supply

USB and Ethernet:

  • Gigabit Ethernet PHY

  • USB-JTAG programming circuit

  • USB-UART bridge

  • USB OTG PHY (host only)

Audio and video:

  • 3.5mm with 24bit DAC and I2S protocol

  • TRRS jack

  • 3.5mm line input jack

  • HDMI receiving port (input)

  • HDMI source port (output)

Switches, buttons, and LEDs:

  • 4 buttons

  • 2 slide switches

  • 4 LEDs

  • 2 RGB LEDs

Expansion connector:

  • Two standard Pmod ports

  • 16 FPGA I/O interfaces (share 8 Pins with Raspberry Pi interface)

  • Arduino shield connector

  • 24 FPGA I/O

  • 6 single-ended 0-3.3V analog inputs of XADC

  • Raspberry Pi connector

  • 28 FPGA I/O (8 shared with Pmod A interface)

  • Low latency control


<< Previous: Basic knowledge of FPGA architecture and applications

<< Next: Xilinx FPGA architecture and classification

Hot News

ASSOCIATED PRODUCTS

  • XA3S500E-4FTG256Q

    XA3S500E-4FTG256Q

    FPGA XA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V Automotive 256-Pin FTBGA

  • XCF08PFSG48C

    XCF08PFSG48C

    FPGA Configuration Flash Memory

  • XA95144XL-15CSG144I

    XA95144XL-15CSG144I

    CPLD XA9500XL Family 3.2K Gates 144 Macro Cells 64.5MHz 0.35um, CMOS Technology 3.3V Automotive 144-Pin CSBGA

  • XA9572XL-15TQG100Q

    XA9572XL-15TQG100Q

    CPLD XA9500XL Family 1.6K Gates 72 Macro Cells 64.5MHz 0.35um Technology 3.3V Automotive 100-Pin TQFP

  • XA9572XL-15VQG64Q

    XA9572XL-15VQG64Q

    CPLD XA9500XL Family 1.6K Gates 72 Macro Cells 64.5MHz 0.35um Technology 3.3V Automotive 64-Pin VTQFP

Lattice FPGA
Need Help?

Support

If you have any questions about the product and related issues, Please contact us.