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Home > FPGA Technology > FPGA > 2 ways to integrate FPGAs: Embedded FPGAs (SoC) and FPGA Chiplets (SiP) - FPGA Technology

2 ways to integrate FPGAs: Embedded FPGAs (SoC) and FPGA Chiplets (SiP)

Date: Dec 06, 2021

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FPGAs are widely popular in systems for its flexibility and adaptability. Increasingly, it is being used in high volume applications, As volumes grow, system designers can consider integration of the FPGA into an SoC to reduce cost, reduce power and/or improve performance.

FPGAs are distinguished by their great flexibility and adaptability. System designers are increasingly considering integrating the FPGA into an SoC to reduce power and improve performance when designing high-volume complex applications.

There are two options for integrating FPGAs into an SoC:o FPGA chiplets, which replace the power hungry SERDES/PHYs with special die-to-die interconnects to communicate with the companion SoC dieo eFPGA, which is an IP block that is put on the SoC dieHow do these alternatives compare? 'll see, it depends on the application and the priorities.

There are several applications where integrating an FPGA has advantages:1. In an existing system where an FPGA is paired with an SoC, for example a Smart To provide flexibility for an SoC to change algorithms and/or protocols as standards change or for the needs of different To provide flexibility for an SoC to change algorithms and/or protocols as standards change or for the needs of different customers3.Acceleration for SoCs where critical workloads run faster on parallel FPGAs than processors4. To provide programmable state machines in architectures that have arrays of compute elements, such as many new AI accelerators

The benefits of integrating FPGAs into SoCs are obvious: 1. To further improve integration and performance for existing FPGA SoC systems, such as SmartNIC smart network card solutions or in the Microsoft Azure cloud. 2. To give SoCs that are not otherwise flexible some programmability, allowing end users to modify protocols and algorithms as requirements change. 3. SoC provides an acceleration core to offload some workloads suitable for FPGA parallel computing to FPGA. 4. Provide programmable state machines and other computing units in SoC architecture as new AI engines. In a word, all the benefits that FPGAs have can be inherited by SoC integration.

eFPGA (SoC) & cFPGA (SiP)

The two popular integration schemes are embedded FPGA (hereinafter referred to as eFPGA integration scheme) and FPGA Chiplets (hereinafter referred to as cFPGA integration scheme) 1. eFPGA integration scheme eFPGA is an FPGA IP core embedded in SoC, either soft or hard core, and the process node often needs to be consistent with SoC .

1Framework of eFPGA.png

Framework of eFPGA

2The eFPGA concept.png

The eFPGA concept

eFPGAs typically have more inputs and outputs than traditional FPGAs, and can be connected to buses, data paths, control paths, PHYs, and other components. This technology was proposed in academia many years ago, but only in the last 5 years has it become widely accepted, and a series of companies focused on eFPGAs have emerged in the US, France, and China to successfully commercialize them. cFPGA integration solution Chiplet was first conceptualized from DARPA's CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) project. It is a die-to-die internal interconnection technology to package multiple module chips with the underlying base chip to form a multi-functional heterogeneous System in Package (SiP) chip model. Theoretically, this technology is a short-cycle, low-cost integration of third-party chips (e.g., I/O, memory chips, NPUs, etc.), and the process nodes can be different for each modular chip. chiplets are one of several efforts by the industry to compensate for the slowing growth of silicon process technology. They originated as multi-chip modules and were born in the 1970s. To date, a number of companies have created their own Chiplet ecosystems early on, including Marvell, AMD, Intel, and others.


3Chiplet's Framework.png

     Chiplet's Framework

4Chiplet concept.png

Chiplet concept

The power-hungry high speed SERDES are the connectivity tiles in this diagram. EMIB is Intel's proprietary wide-bus high bandwidth chip- to-chip interconnect. The FPGA chiplet in the middle is primarily digital logic. Intel and Xilinx will, for certain customers at least, provide die for Intel and Xilinx will, for certain customers at least, provide die for integration into SoCs using interposers, see an example below:    

5integration .png

Intel interposers (from Intel) In this way, an SoC and an FPGA chiplet can be co-packaged with a wide, high speed bus connecting them. Intel has given its own chiplet interconnect technology a fancy name: "Embedded Multi-die Interconnect Bridge" EMIB (shown above), which is a mix of SoC and SiP technologies. Xilinx has been using inter-die interconnect technology since the 7 Series to achieve the convergence of large logic capacity, Serdes high-speed interfaces, and HBM high-bandwidth storage in a limited area through stacking.

6Xilinx Inter-Chip Interconnect Technology History.png

Xilinx Inter-Chip Interconnect Technology History (from Xilinx)

Pros and cons of cFPGA vs eFPGA

Comparison of the pros and cons of the two solutions (since the author of the original article is the CEO of FlexLogix, the article also tends to emphasize the benefits of eFPGAs)

The disadvantages of the chiplet approach are:o the high cost of multi-die packaging using substrateso the need to use a specialized die-to-die The disadvantages of the chiplet approach are:o the high cost of multi-die packaging using substrateso the need to use a specialized die-to-die interface on your SoC that you may not be familiar with or are unable to get from your PHY IP suppliero the smallest FPGA chiplets available still have a large The applications where eFPGA may be a better solution are:o those where the die cost of eFPGA+SoC is lower than the cost of the interposer than the cost of the interposer and chiplet+SoCo those where the amount of eFPGA required is 10s of thousands of LUTs: such small chiplets are not available and the die area required on the SoC is minimalo architectures where eFPGA is distributed across the die in many locations, such as in an array of compute elements where the eFPGA is a programmable state machine for local control of high speed compute blocks: chiplets are really only practical for a single large block of FPGAs

Advantages of the cFPGA SiP solution.

1. Supports inter-chip fusion of multiple process nodes.

2. Designed to create standardized, modular IP, so the FPGA part is usually a fixed chip module and SiP designs are faster to reconfigure and iterate.

Advantages of eFPGA SoC solutions.

1. No need to go through SoC inter-chip interconnect technologies that you may not be familiar with (sometimes not available from your PHY IP provider).

2. Eliminates the need for costly multi-chip package substrates.

3. Designed to enhance the customizability of FPGAs and be more flexible in terms of personalized details customization.

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