The On-Chip Memory (OCM) module contains 256 KB RAM and 128 KB ROM (BootROM), which supports two 64-bit AXI slave interface ports, one dedicated to CPU/ACP access via the APU Supervisor Control Unit (SCU) and the other shared by the Processing System (PS) and all other bus master...
Date: Jul 20, 2021
The design of digital circuits usually requires special handling when it comes to cross-clock domain (CDC) circuits, such as synchronizers, asynchronous FIFOs, and so on. So why CDC needs special treatment, and what problems will result if it is not done.
Date: Jul 12, 2021
The Quad-SPI flash controller is part of an input/output peripheral (IOP) located within the PS that is used to access multi-bit serial flash devices for high throughput and low pin count applications. The controller operates in one of three modes.
Date: Jul 05, 2021
The DMA controller (DMAC) uses a 64-bit AXI host interface running at the CPU_2x clock rate to perform DMA data transfers to and from system memory and PL peripherals. The transfers are controlled by a DMA instruction execution engine that runs on a small instruction set that pro...
Date: Jun 28, 2021
FPGA (Field-Programmable Gate Array), or Field-Programmable Gate Array, is the product of further development based on programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), which solves...
Date: Jun 21, 2021
Only when you build a logic model in your mind and understand the basis of FPGA internal logic structure implementation, you can understand why the overall idea of writing Verilog and writing C is different, and you can understand the difference in design methods between sequenti...
Date: Jun 15, 2021
The TTC contains three independent timers/counters and two TTC modules in the PS, for a total of six timers/counters. The TTC 1 controller can be configured for secure or non-secure mode using the nic301_addr_region_ctrl_registers.security_apb [ttc1_apb] register. The three timer...
Date: Jun 07, 2021
The SD/SDIO controller can communicate with SDIO devices, SD memory cards and MMC cards with four data lines in the following ways. On the SD interface, one (DAT0) or four (DAT0-DAT3) lines can be used for data transfer.
Date: May 31, 2021
This article focuses on the system-level interrupt environment and interrupt function controller. The PS is based on the ARM architecture and utilizes two Cortex-A9 processors (CPUs) and the GIC pl390 interrupt controller.
Date: May 24, 2021
Before learning a technology we often start from its programming language, for example, when learning microcontroller, we often start from assembly or C language. So many developers who start to contact FPGA, often start from VHDL or Verilog to learn. But I personally think that ...
Date: May 18, 2021