QL8X12B-QPF100C of QuickLogic pASIC 1 Family

QL8X12B-QPF100C FPGAs Overview

The pASIC 1 Family is a very-high-speed CMOS user-programmable ASIC devices. The 768 logic cell field-programmable gate array (FPGA) features 22,000 usable PLD gates of high-performance general-purpose logic in a 208-pin PQFP and CQFP package.

Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today’s fastest microprocessors and DSPs.

Features

■ Total of 180 I/O pins
■ -172 Bidirectional Input/Output pins
■ -6 Dedicated Input/High-Drive pins
■ -2 Clock/Dedicated input pins with fanoutindependent, low-skew clock networks
■ -PCI 2.1 Compliant I/Os
■ Input + logic cell + output delays under 6 ns
■ Chip-to-chip operating frequencies up to 110 MHz
■ Internal state machine frequencies up to 150 MHz
■ Clock skew < 0.5 ns
■ Input hysteresis provides high noise immunity
■ Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming
■ 208 pin PQFP pin for pin compatible with the 208 CQFP
■ 0.65µ CMOS process with ViaLink programming technology

FAQ

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Q: How to obtain QL8X12B-QPF100C technical support documents?
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