QL7100-6PQ208 of QuickLogic EclipsePlus Family

QL7100-6PQ208 FPGAs Overview

Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively— these functions require high logic cell usage while garnering only moderate performance results.

The EclipsePlus Family architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the device can address various arithmetic functions efficiently.

Features

Flexible Programmable Logic
• 0.25 µm five layer metal CMOS process
• 2.5 V VCC, 2.5/3.3 V drive capable I/O
• Up to 4,032 logic cells
• Up to 583,008 system gates
• Up to 347 I/O pins
Embedded Dual-Port SRAM
• Up to thirty-six 2,304-bit dual-port high performance SRAM blocks
• Up to 82,900 RAM bits
• RAM/ROM/FIFO wizard for automatic configuration
• Configurable and cascadable
Programmable I/O
• High performance enhanced I/O (EIO)—less than 3 ns Tco
• Programmable slew rate control
• Programmable I/O standards:
LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3
Eight independent I/O banks
Three register configurations: input, output, and output enable

FAQ

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Q: How can I obtain software development tools related to the QuickLogic FPGA platform?
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Q: Where can I purchase QuickLogic QL7100 Development Boards, Evaluation Boards, or EclipsePlus Starter Kit? also provide technical information?
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Q: How to obtain QL7100-6PQ208 technical support documents?
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