QL2P150-7PUN121C of QuickLogic PolarPro II Family

QL2P150-7PUN121C FPGAs Overview

As low as TBD µA 0.18 µm, six layer metal CMOS process 1.8 V core voltage, 1.8/2.5/3.3 V drive capable I/Os to 27 kilobits of SRAM to 85 I/Os available to 150,000 system gates Nonvolatile, instant-on IEEE 1149.1 boundary scan testing compliant
20 quad clock networks per device 4 quad clock networks per quadrant 1 dedicated clock network per quadrant
QuickLogic PolarPro II has a special VLP pin which can enable a low power sleep mode that significantly reduces the overall power consumption of the device by placing the device in standby Enter VLP mode from normal operation in less than 10 µs (typical) Exit from VLP mode to normal operation in less than 10 µs (typical)
Up to four dual-port 4-kilobit and four 2-kilobit high performance SRAM blocks True dual-port capability for RAM and FIFOs Embedded synchronous/asynchronous FIFO controller Configurable and cascadable aspect ratio
There are several security links to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs.
Bank programmable slew rate control Eight independent I/O banks capable of supporting multiple I/O standards in one device Bank programmable I/O standards: LVTTL, LVCMOS, LVCMOS18, and PCI
The QuickLogic PolarPro II is fabricated a 0.18µ, six layer metal CMOS process. The core voltage 1.8 V. The I/O voltage input tolerance and output drive can be set 2.5 V, and 3.3 V.
The QuickLogic PolarPro II logic cell structure presented in Figure is a single register, multiplexer-based logic cell. It is designed for wide fan-in and multiple, simultaneous output functions. The cell has a high fan-in, fits a wide range of functions with to 24 simultaneous inputs (including register control lines), and four outputs (three combinatorial and one registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay. The QuickLogic PolarPro II logic cell can implement: Two independent 3-input functions Any 4-input function to 1 mux function Independent to 1 mux function Single dedicated register with clock enable, active high set and reset signals Direct input selection to the register, which allows combinatorial and register logic to be used separately Combinatorial logic that can also be configured as an edge-triggered master-slave D flip-flop

Features

Low Power Programmable Logic
• Up to 27 customizable building blocks (CBBs) for a detailed explanation of CBBs)
• Up to 27 kilobits of SRAM
• One user configurable clock manager (CCM)
• As low as 4.2 µA standby current
• 0.18 µm, six layer metal CMOS process
• 1.5 V or 1.8 V core voltage, 1.8/2.5/3.3 V drive capable I/Os
• Up to 103 I/Os available
• Up to 150,000 system gates
• Nonvolatile, instant-on
• IEEE 1149.1 boundary scan testing compliant
Embedded Dual-Port SRAM
• Up to four dual-port 4-kilobit and four 2-kilobit high performance SRAM blocks
• True dual-port capability for RAM and FIFOs
• Embedded synchronous/asynchronous FIFO controller
• Configurable and cascadable aspect ratio
Programmable I/O
• Individual programmable slew rate control
• Eight independent I/O banks capable of supporting multiple I/O standards in one device
• Bank programmable I/O standards: LVTTL,

FAQ

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