SII164CTG64 of Lattice

SII164CTG64 FPGAs Overview

The SiI164 transmitter uses VastLane Digital technology to support displays ranging from VGA to UXGA resolutions (25 - 165Mpps) in a single link interface. It has a highly flexible interface with either a 12-bit mode or 24-bit mode for true color (16.7 million) support. Click to enlargeScaleable Bandwidth from 25 to 165 MHz (VGA to UXGA) Flexible Graphics Controller Interface - 12-bit (½ pixel) or 24-bit mode 1 pixel/clock inputs Flexible Input Clocking - single clock single edge (24-bit) or Single clock dual edge (12-/24-bit) or Dual clock single edge (12-bit) I2C Slave Programming Interface Low Voltage Interface - 3.3V with option for 1.0 to 1.8V Receiver Detection - supports Hot Plug Detection De-skewing Option - varies clock to data timing Low Power - 3.3V core operation and power down mode Cable Distant Support - up to 5m with twisted-pair (as per DVI), fiber-optics ready Standards Compliant with DVI 1.0 (DVI is backwards compliant with VESA, P&D and DFP) Package - 64-pin TQFP

FAQ

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Q: How can I obtain software development tools related to the Lattice FPGA platform?
Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase SII164CTG64 Development Boards, Evaluation Boards, or Starter Kit? also provide technical information?
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Q: How to obtain SII164CTG64 technical support documents?
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