PALCE22V10Z-25SI of Lattice PALCE22V10 Family

PALCE22V10Z-25SI FPGAs Overview

The PALCE22V10Z-25SI provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count.

The PALCE22V10Z is an advanced PAL device built with zero-power, high-speed, electricallyerasable CMOS technology. It provides user-programmable logic for replacing conventional zeropower CMOS SSI/MSI gates and flip-flops at a reduced chip count.

The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby current, the PALCE22V10Z allows battery-powered operation for an extended period.

The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs.

The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active-high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell.

The Lattice PALCE22V10 Family series PALCE22V10Z-25SI is Hook-Up Wire; Conductor Size AWG:18; No. Strands x Strand Size:19 x 30; Jacket Color:Yellow; Approval Bodies:UL; Approval Categories:UL AWM Style 1180; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/5 Type EE RoHS Compliant: Yes, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features

◆ As fast as 5-ns propagation delay and 142.8 MHz fMAX (external)

◆ Low-power EE CMOS

◆ 10 macrocells programmable as registered or combinatorial, and active high or active low to match application needs

◆ Varied product term distribution allows up to 16 product terms per output for complex functions

◆ Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)

◆ Global asynchronous reset and synchronous preset for initialization

◆ Power-up reset for initialization and register preload for testability

◆ Extensive third-party software and programmer support

◆ 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC

◆ 5-ns and 7.5-ns versions utilize split leadframes for improved performance

FAQ

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Q: Where can I purchase Lattice PALCE22V10 Development Boards, Evaluation Boards, or PALCE22V10 Starter Kit? also provide technical information?
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Q: How to obtain PALCE22V10Z-25SI technical support documents?
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Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the PALCE22V10Z-25SI pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.