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ORT8850L-1BMN680I

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ORT8850L-1BMN680I

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$4.08 - $97 /Piece | 1 Piece/Pieces (Min. Order)

Lattice

BGA-680

Obsolete

Factory Excess Stock / Franchised Distributor

Programmable Logic ICs

FPGA ORCA Series 4 Family 397K Gates 4992 Cells 0.16um Technology 3.3V 680-Pin BGA

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ORT8850L-1BMN680I FPGAs Overview

Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Programmable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with highspeed serial backplane data transfer. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORT8850L-1BMN680I is made up of backplane transceivers (SERDES) containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-independent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for HDLC for Internet Protocol (IP), designers can build a configurable interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge using our PCI soft core.

The ORT8850L-1BMN680I device offers a clockless High-Speed Interface for inter-device communication on a board or across a backplane. The built-in clock recovery of the ORT8850L-1BMN680I allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required.

The Lattice Programmable Logic ICs series ORT8850L-1BMN680I is FPGA - Field Programmable Gate Array 4992 LUT 278 I/O, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features

Embedded Core Features

• Implemented in an ORCA Series 4 FPGA.

• Allows a wide range of high-speed backplane applications, including SONET transport and termination.
• No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz—106 MHz clock, and a frame pulse.
• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
• Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8 Gbits/s (full duplex).
• HSI function uses Lattice’s 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are supported.
• LVDS I/Os compliant with EIA-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes.
• Low-power 1.5 V HSI core.
• Low-power LVDS buffers.
• Programmable STS-3, and STS-12 framing.
• Independent STS-3, and STS-12 data streams per quad channels.
• 8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic.
• On-chip, Phase-Lock Loop (PLL) clock meets (type B) jitter tolerance specification of ITU-T recommendation G.958.
• Powerdown option of HSI receiver on a per-channel basis.
• HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.
• Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above rates.
• In-band management and configuration through transport overhead extraction/insertion.
• Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted.
• Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.
• Built-in boundry scan (IEEE 1149.1 JTAG).
• FIFOs align incoming data across all eight channels (two groups of four channels or four groups of two channels) for both SONET scrambling. Optional ability to bypass alignment FIFOs.
• 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection
switching applications. STS-192 and above rates are supported through multiple devices.
• ORCA FPGA soft intellectual property core support for a variety of applications.
• Programmable Synchronous Transport Module (STM) pointer mover bypass mode.
• Programmable STM framer bypass mode.
• Programmable Clock and Data Recovery (CDR) bypass mode (clocked LVDS High-Speed Interface).
• Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channelswith redundancy on a single device.
FPGA Features
• High-performance platform design:
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 600K FPGA system gates (ORT8850H).
– Meets multiple I/O interface standards.
– 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
• Traditional I/O selections:
– LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os.
– Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
– Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
– Two slew rates supported (fast and slew-limited).
– Fast-capture input latch and input flip-flop/latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two-input function generator in output path.
• New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, LVPECL.
– LVDS include optional on-chip termination resistor per I/O and on-chip reference generation.
• New capability to (de)multiplex I/O signals:
– New Double-Data Rate (DDR) on both input and output at rates up to 350 MHz (700 Mbits/s effective rate).
– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
• Enhanced twin-quad Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations.
– New register control in each PFU has two independent programmable clocks, clock enables, local SET/RESET, and data selects.
– New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX, and ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing, which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures.
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efficient performance.
• SLIC provides eight 3-State Buffers, up to 10-bit decoder, and PAL-like AND-OR-INVERT (AOI) in each programmable logic cell.
• Improved built-in clock management with dual-output Programmable Phase-Locked Loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possible.

FAQ

  • Q: Does the price of ORT8850L-1BMN680I devices fluctuate frequently?
  • The FPGAkey search engine monitors the ORT8850L-1BMN680I inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for ORT8850L-1BMN680I?
  • No, only submit the quantity, email address and other contact information required for the inquiry of ORT8850L-1BMN680I, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Lattice FPGA platform?
  • Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Lattice ORT8850L Development Boards, Evaluation Boards, or ORCA ORT8850 Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain ORT8850L-1BMN680I technical support documents?
  • Enter the "ORT8850L-1BMN680I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for ORT8850L1BMN680I in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the ORT8850L-1BMN680I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Attributes

  • Operating Supply Voltage

    2.3 V

  • Maximum Operating Temperature

    + 85℃

  • Mounting Style

    SMD/SMT

  • Package / Case

    PBGAM-680

  • Minimum Operating Temperature

    - 40℃

  • Packaging

    Tray

  • Factory Pack Quantity

    120

Technical Documents

  • ORT8850L,H_ORCA Datasheet ORCA ORT8850 Family Data sheet Download>>

Circuit Diagram

ORCA ORT8850 Ordering Information

ORT8850L-1BMN680I PDF Preview

ORT8850L-1BMN680I Tags

  • Lattice ORT8850L
  • ORT8850L development board
  • ORCA ORT8850 evaluation kit
  • Lattice ORCA ORT8850 development board
  • ORCA ORT8850 starter kit
  • ORCA ORT8850 ORT8850L
  • ORT8850L reference design
  • ORT8850L evaluation board
  • ORT8850L-1BMN680I Datasheet PDF

Other Authorized Distributors (Fpgakey will provide Competitive price from all franchised resource.)

  • DISTRIBUTOR
  • PART NUMBER
  • MANUFACTURER
  • DESCRIPTION
  • STOCK
  • PRICE
  • BUY
  • arrow
  • ORT8850L-1BM680C
  • Lattice Semiconductor Corporation
  • 55
  • 1+ $5.3917
    25+ $4.7615

  • arrow
  • ORT8850L-2BM680C
  • Lattice Semiconductor Corporation
  • 128
  • 1+ $83.1984
    10+ $73.4069
    50+ $69.3339
    100+ $41.605

  • arrow
  • ORT8850L-2BMN680C
  • Lattice Semiconductor Corporation
  • 7701
  • 1+ $97.0045
    10+ $95.7324
    50+ $94.4953
    250+ $92.1029
    500+ $89.8271
    1000+ $88.7301
    2500+ $87.6565
    5000+ $86.6178

  • verical
  • ORT8850L-1BM680C
  • LATTICE
  • FPGA ORCA Series 4 Family 397K Gates 4992 Cells 0.16um Technology 3.3V 680-Pin BGA
  • 0
  • 5+ $4.6200
    25+ $4.0800

  • verical
  • ORT8850L-2BM680C
  • LATTICE
  • FPGA ORCA Series 4 Family 397K Gates 4992 Cells 0.16um Technology 3.3V 680-Pin BGA
  • 0
  • 1+ $71.2900
    10+ $62.9000
    50+ $59.4100
    100+ $35.6500

  • verical
  • ORT8850L-2BMN680C
  • LATTICE
  • FPGA ORCA Series 4 Family 397K Gates 4992 Cells 0.16um Technology 3.3V 680-Pin BGA
  • 0
  • 1+ $83.1200
    10+ $82.0300
    50+ $80.9700
    250+ $78.9200
    500+ $76.9700
    1000+ $76.0300
    2500+ $75.1100
    5000+ $74.2200

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