ORSO42G5-2BMN484I of Lattice FPGA ORCA Series 4 Family

ORSO42G5-2BMN484I FPGAs Overview

The ORSO42G5-2BMN484I and ORSO82G5 support a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORSO42G5-2BMN484I and ORSO82G5 allows higher system performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network designers will benefifit from using the backplane transceiver as a network termination device. Sister devices, the ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet (XAUI) and Fibre Channel. The ORSO42G5-2BMN484I and ORSO82G5 perform SONET data scrambling/descrambling, streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to terminate the network into proprietary systems. The cell processing feature in the ORSO42G5-2BMN484I and ORSO82G5 makes them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The ORSO42G5-2BMN484I and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.

The Lattice Programmable Logic ICs series ORSO42G5-2BMN484I is FPGA - Field Programmable Gate Array 10368 LUT 204 I/O, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features

• High-speed SERDES programmable serial data rates of 0.6 Gbps to 2.7 Gbps.

• Asynchronous operation per receive channel (separate PLL per channel).

• Transmit pre-emphasis (programmable) for improved receive data eye opening.

• Provides a 10 Gbps backplane interface to switch fabric using four work and, with the ORSO82G5, four protect 2.5 Gbit/s links. Also supports port cards at rates between 0.6 Gbps and 2.7 Gbps.

• Allows wide range of applications for SONET network termination, as well as generic data moving for high-speed backplane data transfer.

• No knowledge of SONET/SDH needed in generic applications. Simply supply data (75 MHz-168.75 MHz clock) and at least a single frame pulse.

• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.

• Four- or eight-channel HSI functions provide 2.7 Gbps serial user data interface per channel for a total chip bandwidth of >10Gbps or >20 Gbps (full duplex).

• SERDES has low-power CML buffers and support for 1.5V/1.8V I/Os.

• SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.

• Powerdown option of SERDES HSI receiver and/or transmitter on a per-channel basis.

• Ability to mix half-rate and full-rate between the channels with the same reference clock.

• Ability to confifigure each SERDES block independently with its own reference clock.

• STS-48 framing in SONET mode.

• Programmable enable of SONET scrambler/descrambler, A1/A2 insertion and B1 generation and checking.

• Insertion and checking of link assignment values to facilitate interconnection and debugging of backplanes.

• Optional AIS-L insertion during loss-of-frame.

• Optional RDI-L insertion to indicate remote far-end defects for maintenance capabilities.

• SPE signal marks payload bytes in SONET mode.

• Frame alignment across multiple ORSO42G5 and ORSO82G5 devices for work/protect switching at STS-

768/STM-256 and above rates.

• Supports transparent mode where Transport OverHead (TOH) bytes are user-generated in the FPGA.

• Supports two modes of in-band management and confifiguration with TOH byte extraction/insertion by the Embedded core. A1/A2 and B1 insertion can be independently enabled.

– AUTO_SOH where the embedded core inserts the A1/A2 framing bytes, performs the B1 calculation and inserts the B1 byte. All other bytes are passed through unchanged from the FPGA logic as in transparent mode.

– AUTO_TOH where all of the overhead bytes are set by the embedded core. Most of the bytes are set to zero. At the receive side, all of the TOH bytes except those set to a non-zero value can be ignored.

• Optional A1/A2 corruption, B1 byte corruption, and K2 byte corruption for system debug purposes.

• Built-in boundary scan (IEEE 1149.1 and 1149.2 JTAG), including the SERDES interface.

• FIFOs align incoming data across all eight channels (ORSO82G5 only), groups of four channels, or groups of two channels. Optional ability to bypass alignment FIFOs for asynchronous operation between channels is also provided. (Each channel includes its own recovered clock and frame pulse)

FAQ

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Application Field

Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment

ORSO42G5-2BMN484I Specifications

Specification	Value
Operating Supply Voltage	1.5 V
Maximum Operating Temperature	+ 85℃
Mounting Style	SMD/SMT
Package / Case	PBGAM-484
Minimum Operating Temperature	- 40℃
Packaging	Tray
Factory Pack Quantity	300