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Download DatasheetThe MACH 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.
All MACH 4 family members deliver First-Time-Fit and easy system integration with pin-out retention after any design change and refit. For both 3.3-V and 5-V operation, MACH 4 products can deliver guaranteed fixed timing as fast as 7.5 ns tPD and 111 MHz fCNT through the SpeedLocking feature when using up to 20 product terms per output
The Lattice Programmable Logic ICs series M4LV-256/128-12AI is CPLD - Complex Programmable Logic Devices Use ispMACH 4000V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and refit feature
— SpeedLockingTM performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
— 7.5ns tPD Commercial and 10ns tPD Industrial
— 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
◆ Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Bus-FriendlyTM inputs and I/Os
— Programmable security bit
— Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 4
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
— LatticePROTM software for in-system programmability support on PCs and automated test equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General
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| Specification | Value |
|---|---|
| Memory Type | EEPROM |
| Number of Macrocells | 256 |
| Maximum Operating Frequency | 111.1 MHz |
| Delay Time | 12 ns |
| Number of Programmable I/Os | 128 |
| Operating Supply Voltage | 4.5 V to 5.5 V |
| Maximum Operating Temperature | + 85℃ |
| Minimum Operating Temperature | - 40℃ |
| Package / Case | BGA-208 |
| Mounting Style | SMD/SMT |
| Number of Product Terms per Macro | 20 |
| Packaging | Tube |
| Factory Pack Quantity | 40 |
| Supply Voltage - Max | 3.6 V |
| Supply Voltage - Min | 3 V |
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