This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Familis > LatticeSC/M Family > LFSC3GA25E-7FFN1020C-6I

Images are for reference only.


Get Latest Price >

$81.28 - $929 | 1 Pieces(Min. Order)





Factory Excess Stock / Franchised Distributor

LatticeSC/M Family

The LatticeSC family of FPGA combines a high-performance FPGA fabric, high-speed SERDES, high-performance I/Os and large embedded RAM in a single industry leading architecture

Do you want to buy more and get a better price for LFSC3GA25E-7FFN1020C-6I? Please fill in the short form below:

LFSC3GA25E-7FFN1020C-6I FPGAs Overview

The LatticeSC family of FPGA combines a high-performance FPGA fabric, high-speed SERDES, high-performance I/Os and large embedded RAM in a single industry leading architecture. This FPGA family is fabricated in a state of the art technology to provide one of the highest performing FPGAs in the industry.

This family of devices includes features to meet the needs of today’s communication network systems. These features include SERDES with embedded advance PCS (Physical Coding sub-layer), up to 7.8 Mbits of sysMEM embedded block RAM, dedicated logic to support system level standards such as RAPIDIO, HyperTransport, SPI4.2, SFI-4, UTOPIA, XGMII and CSIX. The devices in this family feature clock multiply, divide and phase shift PLLs, numerous DLLs and dynamic glitch free clock MUXs which are required in today’s high end system designs. High speed, high bandwidth I/O make this family ideal for high throughput systems.

The ispLEVER design tool from Lattice allows large complex designs to be efficiently implemented using the LatticeSC family of FPGA devices. Synthesis library support for LatticeSC is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and backannotates it into the design for timing verification.

Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE modules for the LatticeSC family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.

Innovative high-performance FPGA architecture, high-speed SERDES with PCS support, sysMEM embedded memory and high performance I/O are combined in the LatticeSC to provide excellent performance for today’s leading edge systems designs. Table 1-3 details the performance of several common functions implemented within the LatticeSC.


■ High Performance FPGA Fabric

• 15K to 115K four input Look-up Tables (LUT4s)

• 139 to 942 I/Os

• 700MHz global clock; 1GHz edge clocks

■ 4 to 32 High Speed SERDES and flexiPCS (per Device)

• Performance ranging from 600Mbps to 3.8Gbps

• Excellent Rx jitter tolerance (0.8UI at 3.125Gbps)

• Low Tx jitter (0.25UI typical at 3.125Gbps)

• Built-in Pre-emphasis and equalization

• Low power (typically 105mW per channel)

• Embedded Physical Coding Sublayer (PCS) provides pre-engineered implementation for the following standards:

– GbE, XAUI, PCI Express, SONET, Serial RapidIO, 1G Fibre Channel, 2G Fibre Channel

■ 2Gbps High Performance PURESPEED I/O

• Supports the following performance bandwidths

– Differential I/O up to 2Gbps DDR (1GHz Clock)

– Single-ended memory interfaces up to 800Mbps

• 144 Tap programmable Input Delay (INDEL) block on every I/O dynamically aligns data to clock for robust performance

– Dynamic bit Adaptive Input Logic (AIL) monitoring and control circuitry per pin that automatically ensures proper set-up and hold

– Dynamic bus: uses control bus from DLL

– Static per bit

• Electrical standards supported:

– LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL

– SSTL 3/2/18 I, II; HSTL 18/15 I, II


– LVDS, Mini-LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS, Hypertransport

• Programmable On Die Termination (ODT)

– Includes Thevenin Equivalent and low power VTT termination options

■ sysCLOCK Network

• Eight analog PLLs per device

– Frequency range from 15MHz to 1GHz

– Spread spectrum support

• 12 DLLs per device with direct control of I/O delay

– Frequency range from 100MHz to 700MHz

• Extensive clocking network

– 700MHz primary and 325 MHz secondary clocks

– 1GHz I/O-connected edge clocks

• Precision Clock Divider

– Phase matched x2 and x4 division of incoming clocks

• Dynamic Clock Select (DCS)

– Glitch free clock MUX

■ Masked Array for Cost Optimization (MACO) Blocks

• On-chip structured ASIC Blocks provide preengineered IP for low power, low cost system level integration

■ High Performance System Bus

• Ties FPGA elements together with a standard bus framework

– Connects to peripheral user interfaces for run-time dynamic configuration

■ System Level Support

• IEEE standard 1149.1 Boundary Scan, plus ispTRACY internal logic analyzer

• IEEE Standard 1532 in-system configuration

• 1.2V and 1.0V operation

• Onboard oscillator for initialization and general use

• Embedded PowerPC microprocessor interface

• Low cost wire-bond and high pin count flip-chip packaging

• Low cost SPI Flash RAM configuration


  • Q: Does the price of LFSC3GA25E-7FFN1020C-6I devices fluctuate frequently?
  • The FPGAkey search engine monitors the LFSC3GA25E-7FFN1020C-6I inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for LFSC3GA25E-7FFN1020C-6I?
  • No, only submit the quantity, email address and other contact information required for the inquiry of LFSC3GA25E-7FFN1020C-6I, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Lattice FPGA platform?
  • Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Lattice LFSC3GA25 Development Boards, Evaluation Boards, or LatticeSC/M Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain LFSC3GA25E-7FFN1020C-6I technical support documents?
  • Enter the "LFSC3GA25E-7FFN1020C-6I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for LFSC3GA25E7FFN1020C6I in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the LFSC3GA25E-7FFN1020C-6I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Documents

  • LFSC3GA25 LatticeSC/M Family Data sheet Download>>

LFSC3GA25E-7FFN1020C-6I PDF Preview

LFSC3GA25E-7FFN1020C-6I Tags

  • Lattice LFSC3GA25
  • LFSC3GA25 development board
  • LatticeSC/M evaluation kit
  • Lattice LatticeSC/M development board
  • LatticeSC/M starter kit
  • LatticeSC/M LFSC3GA25
  • LFSC3GA25 reference design
  • LFSC3GA25 evaluation board
  • LFSC3GA25E-7FFN1020C-6I Datasheet PDF

Other Authorized Distributors (Fpgakey will provide Competitive price from all franchised resource.)

  • BUY
  • arrow
  • LFSC3GA25E-5F900C
  • Lattice Semiconductor
  • 366
  • 1+ $177.857
    10+ $158.099
    50+ $149.778
    100+ $142.2856
    250+ $94.8571

  • arrow
  • LFSC3GA25E-6F900CAAF
  • Lattice Semiconductor
  • 34
  • 1+ $271.2
    10+ $235.0353

  • arrow
  • LFSC3GA25E-7F900C
  • Lattice Semiconductor
  • 164
  • 1+ $630.3305
    5+ $588.3053
    10+ $551.5319
    25+ $490.2506
    100+ $464.4473

  • arrow
  • LFSC3GA25E-7FFA1020C
  • Lattice Semiconductor
  • 4
  • 1+ $929.2937

  • digikey
  • 0
  • 1+ $286.5074

  • future
  • LFSC3GA25E-5FF1020C
  • Lattice Semiconductor
  • 0
  • 24+ $273.08

  • future
  • LFSC3GA25E-5FF1020I
  • Lattice Semiconductor
  • 0
  • 24+ $314.29

  • future
  • LFSC3GA25E-5FFN1020C
  • Lattice Semiconductor
  • 0
  • 24+ $276.62

  • future
  • LFSC3GA25E-6FF1020C
  • Lattice Semiconductor
  • 0
  • 24+ $314.29

  • future
  • LFSC3GA25E-6FF1020I
  • Lattice Semiconductor
  • 0
  • 24+ $370.51

  • future
  • LFSC3GA25E-6FFN1020C
  • Lattice Semiconductor
  • 0
  • 24+ $314.29

  • future
  • LFSC3GA25E-6FFN1020I
  • Lattice Semiconductor
  • 0
  • 24+ $370.51

  • future
  • LFSC3GA25E-7FF1020C
  • Lattice Semiconductor
  • 0
  • 24+ $370.51

  • verical
  • LFSC3GA25E-5F900C
  • FPGA LatticeSC Family 25000 Cells 90nm Technology 1.2V 900-Pin FBGA Tray
  • 0
  • 1+ $152.4000
    10+ $135.4700
    50+ $128.3400
    100+ $121.9200
    250+ $81.2800

  • verical
  • LFSC3GA25E-6F900CAAF
  • FPGA LatticeSC Family 25000 Cells 90nm Technology 1.2V 900-Pin FBGA
  • 0
  • 1+ $231.5700
    10+ $200.6900

Need Help?


If you have any questions about the product and related issues, Please contact us.