LFE3-150EA-IO-EVN

Features

 Higher Logic Density for Increased System Integration

• 17K to 149K LUTs

• 116 to 586 I/Os  Embedded SERDES

• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes

• Data Rates 230 Mbps to 3.2 Gbps per channel for all other protocols

• Up to 16 channels per device: PCI Express, SONET/SDH, Ethernet (1GbE, SGMII, XAUI), CPRI, SMPTE 3G and Serial RapidIO

 sysDSP

• Fully cascadable slice architecture

• 12 to 160 slices for high performance multiply and accumulate

• Powerful 54-bit ALU operations

• Time Division Multiplexing MAC Sharing

• Rounding and truncation

• Each slice supports

— Half 36x36, two 18x18 or four 9x9 multipliers

— Advanced 18x36 MAC and 18x18 MultiplyMultiply-Accumulate (MMAC) operations

 Flexible Memory Resources

• Up to 6.85Mbits sysMEM Embedded Block RAM (EBR)

• 36K to 303K bits distributed RAM

 sysCLOCK Analog PLLs and DLLs

• Two DLLs and up to ten PLLs per device

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated read/write levelling functionality

• Dedicated gearing logic

• Source synchronous standards support

— ADC/DAC, 7:1 LVDS, XGMII

— High Speed ADC/DAC devices

• Dedicated DDR/DDR2/DDR3 memory with DQS support

• Optional Inter-Symbol Interference (ISI) correction on outputs

 Programmable sysI/O Buffer Supports Wide Range of Interfaces

• On-chip termination

• Optional equalization filter on inputs

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 33/25/18/15 I, II

• HSTL15 I and HSTL18 I, II

• PCI and Differential HSTL, SSTL

• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

 Flexible Device Configuration

• Dedicated bank for configuration I/Os

• SPI boot flash interface

• Dual-boot images supported

• Slave SPI

• TransFR I/O for simple field updates

• Soft Error Detect embedded macro

 System Level Support

• IEEE 1149.1 and IEEE 1532 compliant

• Reveal Logic Analyzer

• ORCAstra FPGA configuration utility

• On-chip oscillator for initialization & general use

• 1.2 V core power supply

FAQ

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• Q: How can I obtain software development tools related to the Lattice FPGA platform?
• Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
• Q: Where can I purchase Lattice LFE3-150 Development Boards, Evaluation Boards, or LatticeECP3 Starter Kit? also provide technical information?
• FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
• Q: How to obtain LFE3-150EA-IO-EVN technical support documents?
• Enter the "LFE3-150EA-IO-EVN" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  
• Q: What should I do if I did not receive the technical support for LFE3150EAIOEVN in time?
• Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the LFE3-150EA-IO-EVN pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.