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Home > FPGA Familis > LatticeECP2/M Family > LFE2M20SE-5FN484C

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$31.765 - $44.118 | 1 Pieces(Min. Order)




Factory Excess Stock / Franchised Distributor

FPGA - Field Programmable Gate Array

FPGA LatticeECP2M Family 19000 Cells 90nm Technology 1.2V 484-Pin FBGA Tray

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LFE2M20SE-5FN484C FPGAs Overview

The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an economical FPGA fabric. This combination was achieved through advances in device architecture and the use of 90nm technology. The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configuration support, including encryption (���S��� versions only) and dual boot capabilities. The LatticeECP2M device family features high speed SERDES with PCS. These high jitter tolerance and low transmission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization settings make SERDES suitable for chip to chip and small form factor backplane applications. Lattice Diamond庐 design software allows large complex designs to be efficiently implemented using the LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP2/M device. The Diamond design tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP2/M family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. The Lattice FPGA - Field Programmable Gate Array series LFE2M20SE-5FN484C is FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERDES DSP -5, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at, and you can also search for other FPGAs products.


■ High Logic Density for System Integration

• 6K to 95K LUTs

• 90 to 583 I/Os

■ Embedded SERDES (LatticeECP2M Only)

• Data Rates 250 Mbps to 3.125 Gbps

• Up to 16 channels per device PCI Express, Ethernet (1GbE, SGMII), OBSAI, CPRI and Serial RapidIO.

■ sysDSP Block

• 3 to 42 blocks for high performance multiply and accumulate

• Each block supports – One 36x36, four 18X18 or eight 9X9 multipliers

■ Flexible Memory Resources

• 55Kbits to 5308Kbits sysMEM Embedded Block RAM (EBR)

– 18Kbit block

– Single, pseudo dual and true dual port

– Byte Enable Mode support

• 12K to 202Kbits distributed RAM

– Single port and pseudo dual port

■ sysCLOCK Analog PLLs and DLLs

• Two GPLLs and up to six SPLLs per device

– Clock multiply, divide, phase & delay adjust

– Dynamic PLL adjustment

• Two general purpose DLLs per device

■ Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated gearing logic

• Source synchronous standards support

– SPI4.2, SFI4 (DDR Mode), XGMII

– High Speed ADC/DAC devices

• Dedicated DDR and DDR2 memory support

– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)

• Dedicated DQS support

■ Programmable sysI/O Buffer Supports Wide Range Of Interfaces

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 3/2/18 I, II

• HSTL15 I and HSTL18 I, II

• PCI and Differential HSTL, SSTL


■ Flexible Device Configuration

• 1149.1 Boundary Scan compliant

• Dedicated bank for configuration I/Os

• SPI boot flash interface

• Dual boot images supported

• TransFR I/O for simple field updates

• Soft Error Detect macro embedded

■ Optional Bitstream Encryption (LatticeECP2/M “S” Versions Only)

■ System Level Support

• ispTRACY internal logic analyzer capability

• On-chip oscillator for initialization & general use

• 1.2V power supply


  • Q: Does the price of LFE2M20SE-5FN484C devices fluctuate frequently?
  • The FPGAkey search engine monitors the LFE2M20SE-5FN484C inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for LFE2M20SE-5FN484C?
  • No, only submit the quantity, email address and other contact information required for the inquiry of LFE2M20SE-5FN484C, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Lattice FPGA platform?
  • Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Lattice LFE2M20 Development Boards, Evaluation Boards, or LatticeECP2/M Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain LFE2M20SE-5FN484C technical support documents?
  • Enter the "LFE2M20SE-5FN484C" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for LFE2M20SE5FN484C in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the LFE2M20SE-5FN484C pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Attributes

  • Number of I/Os


  • Maximum Operating Frequency

    311 MHz

  • Operating Supply Voltage

    1.2 V

  • Maximum Operating Temperature

    + 85℃

  • Mounting Style


  • Package / Case


  • Minimum Operating Temperature

    0 C

  • Packaging


  • Factory Pack Quantity


Technical Documents

  • LFE2M20 LatticeECP2/M Family Data sheet Download>>

Circuit Diagram


LFE2M20SE-5FN484C PDF Preview

LFE2M20SE-5FN484C Tags

  • Lattice LFE2M20
  • LFE2M20 development board
  • LatticeECP2/M evaluation kit
  • Lattice LatticeECP2/M development board
  • LatticeECP2/M starter kit
  • LatticeECP2/M LFE2M20
  • LFE2M20 reference design
  • LFE2M20 evaluation board
  • LFE2M20SE-5FN484C Datasheet PDF

Other Authorized Distributors (Fpgakey will provide Competitive price from all franchised resource.)

  • BUY
  • digikey
  • LFE2M20SE-5FN484C
  • Lattice Semiconductor Corporation
  • IC FPGA 304 I/O 484FBGA
  • 0
  • 60+ $56.7996

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