LFE2M20E-6FN256C-5I of Lattice LatticeECP2/M Family

LFE2M20E-6FN256C-5I FPGAs Overview

The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an economical FPGA fabric. This combination was achieved through advances in device architecture and the use of 90nm technology.

The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configuration support, including encryption (“S” versions only) and dual boot capabilities.

The LatticeECP2M device family features high speed SERDES with PCS. These high jitter tolerance and low transmission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization settings make SERDES suitable for chip to chip and small form factor backplane applications.

The ispLEVER design tool suite from Lattice allows large complex designs to be efficiently implemented using the LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP2/M device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE modules for the LatticeECP2/M family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.

Features

■ High Logic Density for System Integration

• 6K to 95K LUTs

• 90 to 583 I/Os

■ Embedded SERDES (LatticeECP2M Only)

• Data Rates 250 Mbps to 3.125 Gbps

• Up to 16 channels per device PCI Express, Ethernet (1GbE, SGMII), OBSAI, CPRI and Serial RapidIO.

■ sysDSP Block

• 3 to 42 blocks for high performance multiply and accumulate

• Each block supports – One 36x36, four 18X18 or eight 9X9 multipliers

■ Flexible Memory Resources

• 55Kbits to 5308Kbits sysMEM Embedded Block RAM (EBR)

– 18Kbit block

– Single, pseudo dual and true dual port

– Byte Enable Mode support

• 12K to 202Kbits distributed RAM

– Single port and pseudo dual port

■ sysCLOCK Analog PLLs and DLLs

• Two GPLLs and up to six SPLLs per device

– Clock multiply, divide, phase & delay adjust

– Dynamic PLL adjustment

• Two general purpose DLLs per device

■ Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated gearing logic

• Source synchronous standards support

– SPI4.2, SFI4 (DDR Mode), XGMII

– High Speed ADC/DAC devices

• Dedicated DDR and DDR2 memory support

– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)

• Dedicated DQS support

■ Programmable sysI/O Buffer Supports Wide Range Of Interfaces

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 3/2/18 I, II

• HSTL15 I and HSTL18 I, II

• PCI and Differential HSTL, SSTL

• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL

■ Flexible Device Configuration

• 1149.1 Boundary Scan compliant

• Dedicated bank for configuration I/Os

• SPI boot flash interface

• Dual boot images supported

• TransFR I/O for simple field updates

• Soft Error Detect macro embedded

■ Optional Bitstream Encryption (LatticeECP2/M “S” Versions Only)

■ System Level Support

• ispTRACY internal logic analyzer capability

• On-chip oscillator for initialization & general use

• 1.2V power supply

FAQ

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Q: How can I obtain software development tools related to the Lattice FPGA platform?
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