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FPGAKey Technical Documents
Download DatasheetThe LCMXO640-3FTN256C is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip.
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, highsecurity, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs.
The ispLEVER design tools from Lattice allow complex designs to be efficiently implemented using the LCMXO640-3FTN256C device. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools
use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in
the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design
for timing verification.
Non-volatile, Infinitely Reconfigurable
• Instant-on
– powers up in microseconds
• Single chip, no external configuration memory required
• Excellent design security, no bit stream to intercept
• Reconfigure SRAM based logic in milliseconds
• SRAM and non-volatile memory programmable through JTAG port
• Supports background programming of non-volatile memory
Sleep Mode
• Allows up to 100x static current reduction
TransFR Reconfiguration (TFR)
• In-field logic update while system operates
High I/O to Logic Density
• 256 to 2280 LUT4s
• 73 to 271 I/Os with extensive package options
• Density migration supported
• Lead free/RoHS compliant packaging
Embedded and Distributed Memory
• Up to 27.6 Kbits sysMEM Embedded Block RAM
• Up to 7.7 Kbits distributed RAM
• Dedicated FIFO control logic
Flexible I/O Buffer
• Programmable sysIO buffer supports wide range of interfaces:
— LVCMOS 3.3/2.5/1.8/1.5/1.2
— LVTTL
— PCI
— LVDS, Bus-LVDS, LVPECL, RSDS
sysCLOCK PLLs
• Up to two analog PLLs per device
• Clock multiply, divide, and phase shifting
System Level Support
• IEEE Standard 1149.1 Boundary Scan
• Onboard oscillator
• Devices operate with 3.3 V, 2.5 V, 1.8 V or 1.2 V power supply
• IEEE 1532 compliant in-system programming
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
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