LCMXO256C-4MN100C-3I of Lattice MachXO Family

LCMXO256C-4MN100C-3I FPGAs Overview

The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip.

The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, highsecurity, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs.

The ispLEVER design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification.

Features

 Non-volatile, Infinitely Reconfigurable

• Instant-on

– powers up in microseconds

• Single chip, no external configuration memory required

• Excellent design security, no bit stream to intercept

• Reconfigure SRAM based logic in milliseconds

• SRAM and non-volatile memory programmable through JTAG port

• Supports background programming of non-volatile memory

 Sleep Mode

• Allows up to 100x static current reduction

 TransFR Reconfiguration (TFR)

• In-field logic update while system operates

 High I/O to Logic Density

• 256 to 2280 LUT4s

• 73 to 271 I/Os with extensive package options

• Density migration supported

• Lead free/RoHS compliant packaging

 Embedded and Distributed Memory

• Up to 27.6 Kbits sysMEM Embedded Block RAM

• Up to 7.7 Kbits distributed RAM

• Dedicated FIFO control logic

 Flexible I/O Buffer

• Programmable sysIO buffer supports wide range of interfaces:

— LVCMOS 3.3/2.5/1.8/1.5/1.2

— LVTTL

— PCI

— LVDS, Bus-LVDS, LVPECL, RSDS

 sysCLOCK PLLs

• Up to two analog PLLs per device

• Clock multiply, divide, and phase shifting

 System Level Support

• IEEE Standard 1149.1 Boundary Scan

• Onboard oscillator

• Devices operate with 3.3 V, 2.5 V, 1.8 V or 1.2 V power supply

• IEEE 1532 compliant in-system programming

FAQ

Q: Does the price of LCMXO256C-4MN100C-3I devices fluctuate frequently?
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Q: How can I obtain software development tools related to the Lattice FPGA platform?
Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Lattice LCMXO256 Development Boards, Evaluation Boards, or MachXO Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain LCMXO256C-4MN100C-3I technical support documents?
Enter the "LCMXO256C-4MN100C-3I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for LCMXO256C4MN100C3I in time?
Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the LCMXO256C-4MN100C-3I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.