LC5768VG-5F256C-75I of Lattice ispMACH 5000VG Family

LC5768VG-5F256C-75I FPGAs Overview

The LC5768VG-5F256C-75I represents the third generation of Lattice’s SuperWIDE CPLD architecture. Through their wide 68-input blocks, these devices give significantly improved speed performance for typical designs over architectures with fewer inputs.

The LC5768VG-5F256C-75I takes the unique benefits of the SuperWIDE architecture and extends it to higher densities referred to as SuperBIG, by using the combination of an innovative product term architecture and a twotiered hierarchical routing architecture. Additionally, sysCLOCK and sysIO capabilities have been added to maximize system-level performance and integration.

The LC5768VG-5F256C-75I devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) interconnected by a tiered routing system. Figure 1 shows the functional block diagram of the ispMACH 5000VG. Groups of four GLBs, referred to as segments, are interconnected via a Segment Routing Pool (SRP). Segments are interconnected via the Global Routing Pool (GRP.) Together the GLBs and the routing pools allow designers to create large designs in a single device without compromising performance.

Each GLB has 68 inputs coming from the SRP and contains 163 product terms. These product terms form groups of five product term clusters, which feed the PT sharing array or the macrocell directly. The ispMACH 5000VG allows up to 160 product terms to be connected to a single macrocell via the product term expanders and PT Sharing Array.

The macrocell is designed to provide flexible clocking and control functionality with the capability to select between global, product term and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if required, the sysIO cell.

All I/Os in the LC5768VG-5F256C-75I are sysIOs, which are split into four banks. Each bank has a separate I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of today’s emerging interface standards. Within a bank, inputs can be set to a variety of standards, providing the reference voltage requirements of the chosen standards are compatible. Within a bank, the outputs can be set to differing standards, providing the I/O power supply voltage and the reference voltage requirements of the chosen standard are compatible. Support for this wide range of standards allows designers to achieve significantly higher board-level performance compared to the more traditional LVCMOS standards.

The LC5768VG-5F256C-75I devices also contain sysCLOCK Phase Locked Loops (PLLs) that provide designers with increased clocking flexibility. The PLLs can be used to synthesize new clocks for use on-chip or elsewhere within the system. They can also be used to deskew clocks, again both at the chip and system levels. A variable delay line capability further improves this and allows designers to retard or advance the clock in order to tune set-up and clock-to-out times for optimal results. The ispMACH 5000VG Family Selection Guide (Table 1) details the key attributes and packages for the ispMACH 5000VG devices.

Features

■ High Density
• 768 to 1,024 macrocells
• 196 to 384 I/Os
■ sysCLOCK PLL – Timing Control
• Multiply and divide factors between 1 and 32
• Clock shifting capability ± 3.5ns in 500ps steps
• Multiple output frequencies
• External feedback capability for board-level
clock deskew
• LVDS/LVPECL clock input capability
■ High Speed Logic Implementation
• SuperWIDE 68-input logic block
• Up to 160 product terms per output
• Hierarchical routing structure provides fast interconnect
■ sysIO Capability
• LVCMOS 1.8, 2.5 and 3.3
• LVTTL
• SSTL 2 (I & II)
• SSTL 3 (I & II)
• CTT 3.3, CTT 2.5
• HSTL (I & III)
• PCI-X, PCI 3.3
• GTL+
• AGP-1X
• 5V tolerance

• Programmable drive strength

■ Ease of Design
• Product term sharing
• Extensive clocking and OE capability
■ Easy System Integration
• 3.3V power supply
• Hot socketing
• Input pull-up, pull-down or bus-keeper
• Open drain capability
• Slew rate control
• Macrocell-based power management
• IEEE 1149.1 boundary scan testable
• In-system programmable via IEEE 1532 ISC compliant interface

FAQ

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Q: How can I obtain software development tools related to the Lattice FPGA platform?
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Q: Where can I purchase Lattice LC5768VG Development Boards, Evaluation Boards, or ispMACH 5000VG Starter Kit? also provide technical information?
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