LC4064V-72TN100-10I of Lattice ispMACH 4000V/B/C/Z Family

LC4064V-72TN100-10I FPGAs Overview

The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend of Lattice’s two most popular architectures: the ispLSI 2000 and ispMACH 4A. Retaining the best of both families, the LC4064V-72TN100-10I architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family.

The LC4064V-72TN100-10I combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration.

The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters.

The LC4064V-72TN100-10I of ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B) and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LC4064V-72TN100-10I also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/ 2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to VCC (logic core).

Features

■ High Performance

• fMAX = 400MHz maximum operating frequency

• tPD = 2.5ns propagation delay

• Up to four global clock pins with programmable clock polarity control

• Up to 80 PTs per output

■ Ease of Design

• Enhanced macrocells with individual clock, reset, preset and clock enable controls

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-FitTM and refit

• Fast path, SpeedLockingTM Path, and wide-PT path

• Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders

■ Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)

• Typical static current 10µA (4032Z)

• Typical static current 1.3mA (4000C)

• 1.8V core low dynamic power

• ispMACH 4000Z operational down to 1.6V VCC

■ Broad Device Offering

• Multiple temperature range support

– Commercial: 0 to 90°C junction (Tj )

– Industrial: -40 to 105°C junction (Tj )

– Extended: -40 to 130°C junction (Tj )

• For AEC-Q100 compliant devices, refer to LA-ispMACH 4000V/Z Automotive Data Sheet

■ Easy System Integration

• Superior solution for power sensitive consumer applications

• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

• Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Programmable output slew rate

• 3.3V PCI compatible

• IEEE 1149.1 boundary scan testable

• 3.3V/2.5V/1.8V In-System Programmable (ISP) using IEEE 1532 compliant interface

• I/O pins with fast setup path

• Lead-free package options

FAQ

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