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Programmable Power Supply Monitoring, Sequencing and Margining Controller
The Lattice Power Manager II ispPAC-POWR1220AT8 is a general-purpose power-supply monitor, sequence and margin controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2 CMOS technology. The ispPAC-POWR1220AT8 device provides 12 independent analog input channels to monitor up to 12 power supply test points. Each of these input channels offers a differential input to support remote ground sensing, and has two independently programmable comparators to support both high/low and in-bounds/ out-of-bounds (window-compare) monitor functions. Six general-purpose digital inputs are also provided for miscellaneous control functions.
The ispPAC-POWR1220AT8 provides 20 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Four of these outputs (HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can provide up to 12V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.
The ispPAC-POWR1220AT8 incorporates a 48-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using LogiBuilder, an easy-to-learn language integrated into the PAC-Designer software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs.
In addition to the sequence control functions, the ispPAC-POWR1220AT8 incorporates eight DACs for generating trimming voltage to control the output voltage of a DC-DC converter. The trimming voltage can be set to four hardware selectable preset values (voltage profiles) or can be dynamically loaded in to the DAC through the I2 C bus. Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode. The operating voltage profile can either be selected using external hardware pins or through the PLD outputs.
The on-chip 10-bit A/D converter can both be used to monitor the VMON voltage through the I2 C bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the ispPAC-POWR1220AT8 device.
The I2 C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON inputs, read back the status of each of the VMON comparator and PLD outputs, control logic signals IN2 to IN5, control the output pins, and load the DACs for the generation of the trimming voltage of the external DC-DC converter.The Lattice PAD series ISPPAC-POWR1220AT8 is In-System Programmable Power Supply Monitoring, Sequencing and Margining Controller, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.
Monitor, Control, and Margin Multiple Power Supplies
• Simultaneously monitors up to 12 power supplies
• Provides up to 20 output control signals
• Provides up to eight analog outputs for margining/trimming power supply voltages
• Programmable digital and analog circuitry
Power Supply Margin and Trim Functions
• Trim and margin up to eight power supplies
• Dynamic voltage control through I2 C
• Four hardware selectable voltage profiles
• Independent Digital Closed-Loop Trim function for each output
Embedded PLD for Sequence Control
• 48-macrocell CPLD implements both state machines and combinatorial logic functions
Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
Analog Input Monitoring
• 12 independent analog monitor inputs
• Differential inputs for remote ground sense
• Two programmable threshold comparators per analog input
• Hardware window comparison
• 10-bit ADC for I2 C monitoring
High-Voltage FET Drivers
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or digital output
2-Wire (I2 C/SMBus Compatible) Interface
• Comparator status monitor
• ADC readout
• Direct control of inputs and outputs
• Power sequence control
• Dynamic trimming/margining control
3.3V Operation, Wide Supply Range 2.8V to 3.96V
• In-system programmable through JTAG
• Industrial temperature range: -40°C to +85°C
• 100-pin TQFP package, lead-free option
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