ISPPAC-CLK5610V-01T48C

Features

■ 10MHz to 320MHz Input/Output Operation

■ Low Output to Output Skew (<50ps)

■ Low Jitter Peak-to-Peak (<60ps)

■ Up to 20 Programmable Fan-out Buffers

• Programmable output standards and individual enable controls

- LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL

• Programmable output impedance

- 40 to 70Ω in 5Ω increments

• Programmable slew rate

• Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V

■ Fully Integrated High-Performance PLL

• Programmable lock detect

• Multiply and divide ratio controlled by

- Input divider (5 bits)

- Feedback divider (5 bits)

- Five output dividers (5 bits)

• Programmable On-chip Loop Filter

■ Precision Programmable Phase Adjustment (Skew) Per Output

• 16 settings; minimum step size 195ps

- Locked to VCO frequency

• Up to +/- 12ns skew range

• Coarse and fine adjustment modes

■ Up to Five Clock Frequency Domains

■ Flexible Clock Reference and External Feedback Inputs

• Programmable input standards

- LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL

• Clock A/B selection multiplexer

• Feedback A/B selection multiplexer

• Programmable termination

■ Four User-programmable Profiles Stored in E2 CMOS Memory

• Supports both test and multiple operating configurations

■ Full JTAG Boundary Scan Test In-System Programming Support

■ Exceptional Power Supply Noise Immunity

■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges

■ 100-pin and 48-pin TQFP Packages

Applications

FAQ

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• FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
• Q: How to obtain ISPPAC-CLK5610V-01T48C technical support documents?
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