ISPPAC-CLK5510V-01TN48I

Features

■ 10MHz to 320MHz Input/Output Operation

■ Low Output to Output Skew (<50ps)

■ Low Jitter Peak-to-Peak(<70ps)

■ Up to 20 Programmable Fan-out Buffers

• Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL

• Programmable precision output impedance - 40 to 70Ω in 5Ω increments

• Programmable slew rate

• Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V

■ Fully Integrated High-Performance PLL

• Programmable lock detect

• Multiply and divide ratio controlled by - Input divider (5 bits) - Internal feedback divider (5 bits) - Five output dividers (5 bits)

• Programmable On-chip Loop Filter

■ Precision Programmable Phase Adjustment (Skew) Per Output

• 16 settings; minimum step size 195ps - Locked to VCO frequency

• Up to +/- 12ns skew range

• Coarse and fine adjustment modes

■ Up to Five Clock Frequency Domains

■ Flexible Clock Reference Inputs

• Programmable input standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL

• Clock A/B selection multiplexer

• Programmable precision termination

■ Four User-programmable Profiles Stored in E2 CMOS Memory

• Supports both test and multiple operating configurations

■ Full JTAG Boundary Scan Test In-System Programming Support

■ Exceptional Power Supply Noise Immunity

■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges

■ 100-pin and 48-pin TQFP Packages

■ Applications

• Circuit board common clock generation and distribution • PLL-based frequency generation • High fan-out clock buffer

FAQ

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• Q: How can I obtain software development tools related to the Lattice FPGA platform?
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• Q: Where can I purchase Lattice ISPPAC-CLK5510 Development Boards, Evaluation Boards, or ispClock 5500 Starter Kit? also provide technical information?
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• Q: How to obtain ISPPAC-CLK5510V-01TN48I technical support documents?
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