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Home > FPGA Familis > ispClock 5300S Family > ISPPAC-CLK5320S-01TN64I

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$5.175 - $5.750 | 1 Pieces(Min. Order)

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Product Categories:
Clock & Timer ICs
Zero Delay Buffer 20-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 64-Pin TQFP Tray
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ISPPAC-CLK5320S-01TN64I FPGAs Overview

ISPPAC-CLK5320S-01TN64I Lattice Semiconductor Corporation, IC BUFFER FANOUT 20OUTPUT 64TQFP

Zero Delay Buffer 20-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 64-Pin TQFP Tray
Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I The Lattice Clock & Timer ICs series ISPPAC-CLK5320S-01TN64I is Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at, and you can also search for other FPGAs products.


                                                   ■ Four Operating Configurations
• Zero delay buffer
• Zero delay and non-zero delay buffer
• Dual non-zero delay buffer
• Non-zero delay buffer with output divider
■ 8MHz to 267MHz Input/Output Operation
■ Low Output to Output Skew (<100ps)
■ Low Jitter Peak-to-Peak (< 70 ps)
■ Up to 20 Programmable Fan-out Buffers
• Programmable single-ended output standards and individual enable controls
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■ Fully Integrated High-Performance PLL
• Programmable lock detect
• Three “Power of 2” output dividers (5-bit)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
• Internal/external feedback
■ Precision Programmable Phase Adjustment
(Skew) Per Output
• 8 settings; minimum step size 156ps
- Locked to VCO frequency
• Up to +/- 5ns skew range
• Coarse and fine adjustment modes
■ Up to Three Clock Frequency Domains
■ Flexible Clock Reference and External Feedback Inputs
• Programmable single-ended or differential input reference standards
LVPECL, Differential HSTL, Differential SSTL
• Clock A/B selection multiplexer
• Programmable Feedback Standards
• Programmable termination
■ All Inputs and Outputs are Hot Socket Compliant
■ Full JTAG Boundary Scan Test In-System Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
■ 48-pin and 64-pin TQFP Packages


                                                   • Circuit board common clock distribution
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer


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  • Q: How can I obtain software development tools related to the Lattice FPGA platform?
  • Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Lattice ispPAC-CLK5320S Development Boards, Evaluation Boards, or ispClock 5300S Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain ISPPAC-CLK5320S-01TN64I technical support documents?
  • Enter the "ISPPAC-CLK5320S-01TN64I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
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  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the ISPPAC-CLK5320S-01TN64I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

ISPPAC-CLK5320S-01TN64I Specifications

Specification Value
Maximum Operating Temperature + 85℃
Package / Case TQFP-64
Packaging Tray
Minimum Operating Temperature - 40℃
Mounting Style SMD/SMT
Factory Pack Quantity 800

Technical Documents

  • ispClock5300S Family Data Sheet ispClock 5300S Family Data sheet Download>>

Circuit Diagram

ispClock5300S Family Functional Diagram

ISPPAC-CLK5320S-01TN64I PDF Preview

ISPPAC-CLK5320S-01TN64I Tags

  • Lattice ispPAC-CLK5320S
  • ispPAC-CLK5320S development board
  • ispClock 5300S evaluation kit
  • Lattice ispClock 5300S development board
  • ispClock 5300S starter kit
  • ispClock 5300S ispPAC-CLK5320S
  • ispPAC-CLK5320S reference design
  • ispPAC-CLK5320S evaluation board
  • ISPPAC-CLK5320S-01TN64I Datasheet PDF

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