ISPLSI5512VE-80LF388I FPGAs Overview
ISPLSI 5512VE-80LF388I Lattice Semiconductor Corporation, IC CPLD 512MC 12NS 388FBGA
Features
• Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 6000 PLD Gates / 128 Macrocells
— 96 I/O Pins Available
— 128 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2 CMOS TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell
FAQ
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Q: How can I obtain software development tools related to the Lattice FPGA platform?
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Q: How to obtain ISPLSI5512VE-80LF388I technical support documents?
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Enter the "ISPLSI5512VE-80LF388I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
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Q: What should I do if I did not receive the technical support for ISPLSI5512VE80LF388I in time?
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Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the ISPLSI5512VE-80LF388I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.
Application Field
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Artificial Intelligence
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5G Technology
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Cloud Computing
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Consumer Electronics
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Wireless Technology
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Industrial Control
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Internet of Things
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Medical Equipment
ISPLSI5512VE-80LF388I Specifications
Specification |
Value |
Memory Type |
EEPROM |
Number of Macrocells |
512 |
Maximum Operating Frequency |
80 MHz |
Delay Time |
6.5 ns |
Number of Programmable I/Os |
100 |
Operating Supply Voltage |
3.3 V |
Maximum Operating Temperature |
+ 105 C |
Minimum Operating Temperature |
- 40℃ |
Package / Case |
BGA-272 |
Mounting Style |
SMD/SMT |
Number of Product Terms per Macro |
35 |
Supply Voltage - Max |
3.6 V |
Supply Voltage - Min |
3 V |