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Home > FPGA Familis > SuperWIDE High Density PLD > ISPLSI5128VE100LTN128-100I

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SuperWIDE High Density PLD

In-System Programmable 3.3V SuperWIDE High Density PLD

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ISPLSI5128VE100LTN128-100I FPGAs Overview

The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.

Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable.

The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, combinatorial and registered. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to construct high-speed input registers.

Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also available to each register, eliminating the need to gate the clock to the macrocell registers. Reset for the macrocell register is provided from the global signal, its polarity is userselectable. The macrocell register can be programmed to operate as a D-type register or a D-type latch.

The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one input from each macrocell output and one input from each I/O pin.

The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows individual output drivers to drive either 3.3V (from the device VCC) or 2.5V (from the VCCIO pin) output levels while the device logic and the output current drive are powered from device supply (VCC). The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs. Additionally, a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device.

The ispLSI 5000VE Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface.

An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction.


— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 6000 PLD Gates / 128 Macrocells
— 96 I/O Pins Available
— 128 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— Interfaces with Standard 5V TTL Devices
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell


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  • Q: How can I obtain software development tools related to the Lattice FPGA platform?
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  • Q: Where can I purchase Lattice ispLSI5128VE Development Boards, Evaluation Boards, or SuperWIDE High Density PLD Starter Kit? also provide technical information?
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Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Documents

  • ispLSI5128VE SuperWIDE High Density PLD Family Data sheet Download>>

Circuit Diagram


ISPLSI5128VE100LTN128-100I PDF Preview

ISPLSI5128VE100LTN128-100I Tags

  • Lattice ispLSI5128VE
  • ispLSI5128VE development board
  • SuperWIDE High Density PLD evaluation kit
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  • SuperWIDE High Density PLD starter kit
  • SuperWIDE High Density PLD ispLSI5128VE
  • ispLSI5128VE reference design
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  • ISPLSI5128VE100LTN128-100I Datasheet PDF

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  • ISPLSI5128VE-180LTN128
  • CPLD ispLSI® 5000VE Family 6K Gates 128 Macro Cells 180MHz 3.3V 128-Pin TQFP
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