ISPLSI3448-70LBN432 of Lattice CPLD ispLSI 3000 Family

ISPLSI3448-70LBN432 FPGAs Overview

The ispLSI 3448 is a High-Density Programmable Logic Device containing 672 Registers, 224 Universal I/Os, five Dedicated Clock Inputs, 14 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3448 features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 3448 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 3448 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...N3. There are a total of 56 of these Twin GLBs in the ispLSI 3448 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP.

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 224 I/O

— 20000 PLD Gates

— 672 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH-PERFORMANCE E2 CMOS TECHNOLOGY

— fmax = 90 MHz Maximum Operating Frequency

— tpd = 12 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• ispLSI FEATURES:

— 5V In-System Programmable (ISP) Using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue Logic and Structured Designs

— Enhanced Pin Locking Capability

— Five Dedicated Clock Inputs

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Minimize Switching Noise

— Flexible I/O Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER

— PC and UNIX Platforms

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