ISPLSI3256E-100LB320 of Lattice CPLD ispLSI 3000 Family

ISPLSI3256E-100LB320 FPGAs Overview

The ispLSI 3256E is a High Density Programmable Logic Device containing 512 Registers, 256 Universal I/O pins, five Dedicated Clock Input Pins, 16 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3256E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 3256E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 3256E device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3. There are a total of 32 Twin GLBs in the ispLSI 3256E device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP.

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 256 I/O Pins

— 12000 PLD Gates

— 512 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E2 CMOS TECHNOLOGY

— fmax = 100 MHz Maximum Operating Frequency

— tpd = 10 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 5V In-System Programmable (ISP) using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue Logic and Structured Designs

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER

— PC and UNIX Platforms

FAQ

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