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CPLD ispLSI 3000 Family
CPLD ispLSI 3000 Family 9K Gates 192 Macro Cells 70MHz 5V 240-Pin PQFP
The basic unit of logic on the ispLSI 3192 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...F3. There are a total of 24 of these Twin GLBs in the ispLSI 3192 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP.
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