ISPLSI2128VL-100LB208 of Lattice CPLD ispLSI 2000 Family

ISPLSI2128VL-100LB208 FPGAs Overview

The ispLSI 2128 is a High Density Programmable LogicDevice. The device contains 128 Registers,128 Universal l/O pins, eight Dedicated Input pins, three DedicatedClock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128 features 5V in-system programmabilityand in-system diagnostic capabilities. The ispLSI 2128 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2128 device is the Generic Logic Block（GLB）.The GLBs are labeledA0，A1 .D7（see ISPLSI2128VL-100LB208 Datasheet）.There are a total of 32 GLBs in the ispLSI 2128 device.Each GLB is made up of four macrocells.Each GLB has 18 inputs，a programmable AND/OR/Exclusive OR array，and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs.All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.

Features

·HIGH DENSITY PROGRAMMABLE LOGIC一6000 PLD Gates
—128 I/O Pins，Eight Dedicated Inputs
—128Registers
-High Speed Global Interconnect
-Wide Input Gating for Fast Counters，State Machines，Address Decoders，etc.
一Small Logic Block Size for Random Logic
·HIGH PERFORMANCE ECMOSO TECHNOLOGY
-fmax=100 MHz Maximum Operating Frequency
—tpd=10 ns Propagation Delay一TTL Compatible Inputs and Outputs
-Electrically Erasable and Reprogrammable
-Non-Volatile
—100%Tested at Time of Manufacture

-Unused Product Term Shutdown Saves Power

·IN-SYSTEM PROGRAMMABLE
-In-System Programmable（ISPTM）5V Only
-Increased Manufacturing Yields，Reduced Time-to-
Market and Improved Product Quality一Reprogram Soldered Devices for Faster Prototyping
·OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDS WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
-Complete Programmable Device Can Combine Glue Logic and Structured Designs一Enhanced Pin Locking Capability
-Three Dedicated Clock Input Pins
-Synchronous and Asynchronous Clocks
-Programmable Output Slew Rate Control to Minimize Switching Noise
—Flexible Pin Placement
-Optimized Global Routing Pool Provides Global Interconnectivity
·ispEXPERTTM-LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-Superior Quality of Results
-Tightly Integrated with Leading CAE Vendor Tools
-Productivity Enhancing Timing Analyzer,Explore Tools,Timing Simulator and ispANALYZERTM
-PC and UNIX Platforms

FAQ

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