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ISPLSI2096VL-135LT128I

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ISPLSI2096VL-135LT128I

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$8.747 - $32 | 1 Pieces(Min. Order)

Lattice

TQFP-128-96

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Factory Excess Stock / Franchised Distributor

CPLD - Complex Programmable Logic Devices

CPLD - Complex Programmable Logic Devices USE ispMACH 4000B

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ISPLSI2096VL-135LT128I FPGAs Overview

The ispLSI 2096VL is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VL features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2096VL offers nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2096VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see ISPLSI2096VL-135LT128I Datasheet). There are a total of 24 GLBs in the ispLSI 2096VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.

The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control, and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 3.3V signal levels to support mixed-voltage systems.

Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2096VL device contains three Megablocks.

The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.

Clocks in the ispLSI 2096VL device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the outputs of the ispLSI 2096VL are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration is a totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools.

Features

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V and 2096VE Devices
• 2.5V LOW VOLTAGE 2096 ARCHITECTURE
— Interfaces with Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant)
— 85 mA Typical Active Current
• HIGH PERFORMANCE E2 CMOS TECHNOLOGY
— fmax = 165 MHz Maximum Operating Frequency
— tpd = 5.5 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP) Using Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global Interconnectivity

FAQ

  • Q: Does the price of ISPLSI2096VL-135LT128I devices fluctuate frequently?
  • The FPGAkey search engine monitors the ISPLSI2096VL-135LT128I inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for ISPLSI2096VL-135LT128I?
  • No, only submit the quantity, email address and other contact information required for the inquiry of ISPLSI2096VL-135LT128I, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Lattice FPGA platform?
  • Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Lattice ISPLSI2096VL Development Boards, Evaluation Boards, or SuperFAST High Density PLD Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain ISPLSI2096VL-135LT128I technical support documents?
  • Enter the "ISPLSI2096VL-135LT128I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for ISPLSI2096VL135LT128I in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the ISPLSI2096VL-135LT128I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Attributes

  • Memory Type

    EEPROM

  • Number of Macrocells

    96

  • Maximum Operating Frequency

    135 MHz

  • Delay Time

    7.5 ns

  • Number of Programmable I/Os

    96

  • Operating Supply Voltage

    2.3 V to 2.7 V

  • Maximum Operating Temperature

    + 70 C

  • Minimum Operating Temperature

    0 C

  • Package / Case

    TQFP-128-96

  • Mounting Style

    SMD/SMT

  • Supply Current

    85 mA

  • Supply Voltage - Max

    2.7 V

  • Supply Voltage - Min

    2.3 V

Technical Documents

  • ISPLSI2096VL SuperFAST High Density PLD Family Data sheet Download>>

Circuit Diagram

ISPLSI2096VL
ISPLSI2096VL
ISPLSI2096VL

ISPLSI2096VL-135LT128I PDF Preview

ISPLSI2096VL-135LT128I Tags

  • Lattice ISPLSI2096VL
  • ISPLSI2096VL development board
  • SuperFAST High Density PLD evaluation kit
  • Lattice SuperFAST High Density PLD development board
  • SuperFAST High Density PLD starter kit
  • SuperFAST High Density PLD ISPLSI2096VL
  • ISPLSI2096VL reference design
  • ISPLSI2096VL evaluation board
  • ISPLSI2096VL-135LT128I Datasheet PDF

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