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Home > FPGA Familis > CPLD ispLSI 2000 Family > ISPLSI2064V-60LJ44
ISPLSI2064V-60LJ44

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ISPLSI2064V-60LJ44

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$5.771 - $26 | 1 Pieces(Min. Order)

Lattice

PLCC44

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Factory Excess Stock / Franchised Distributor

CPLD ispLSI 2000 Family

3.3V High Density Programmable Logic

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ISPLSI2064V-60LJ44 FPGAs Overview

The ispLSI 2064V is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Globa lOE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064V features in-system programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2064V offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2064V device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…B7 (see ISPLSI2064V-60LJ44 Datasheet). There are a total of 16 GLBs in the ispLSI 2064V device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.

Features

• HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices

— The 64 I/O Pin Version is Fuse Map Compatible with 5V ispLSI 2064

• HIGH-PERFORMANCE E2 CMOS TECHNOLOGY
— fmax = 100MHz Maximum Operating Frequency
— tpd = 7.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP) Using Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping

• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms

FAQ

  • Q: Does the price of ISPLSI2064V-60LJ44 devices fluctuate frequently?
  • The FPGAkey search engine monitors the ISPLSI2064V-60LJ44 inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
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  • No, only submit the quantity, email address and other contact information required for the inquiry of ISPLSI2064V-60LJ44, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Lattice FPGA platform?
  • Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Lattice ISPLSI2064V Development Boards, Evaluation Boards, or CPLD ispLSI 2000 Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain ISPLSI2064V-60LJ44 technical support documents?
  • Enter the "ISPLSI2064V-60LJ44" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for ISPLSI2064V60LJ44 in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the ISPLSI2064V-60LJ44 pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Documents

  • ISPLSI2064V CPLD ispLSI 2000 Family Data sheet Download>>

Circuit Diagram

ISPLSI2064V
ISPLSI2064V
ISPLSI2064V
ISPLSI2064V

ISPLSI2064V-60LJ44 PDF Preview

ISPLSI2064V-60LJ44 Tags

  • Lattice ISPLSI2064V
  • ISPLSI2064V development board
  • CPLD ispLSI 2000 evaluation kit
  • Lattice CPLD ispLSI 2000 development board
  • CPLD ispLSI 2000 starter kit
  • CPLD ispLSI 2000 ISPLSI2064V
  • ISPLSI2064V reference design
  • ISPLSI2064V evaluation board
  • ISPLSI2064V-60LJ44 Datasheet PDF

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