ISPLSI1032E-50LJ of Lattice CPLD ispLSI 1000 Family

ISPLSI1032E-50LJ FPGAs Overview

The ispLSI 1032 is a High-Density Programmable Logic Device containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 1032 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see ISPLSI1032E-50LJ Datasheet). There are a total of 32 GLBs in the ispLSI 1032 device. Each GLB has 18 inputs, a program mable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— High Speed Global Interconnect

— 6000 PLD Gates

— 64 I/O Pins, Eight Dedicated Inputs

— 192 Registers

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Fast Random Logic

— Security Cell Prevents Unauthorized Copying

• HIGH PERFORMANCE E2CMOS TECHNOLOGY

— fmax = 90 MHz Maximum Operating Frequency

— fmax = 60 MHz for Industrial and Military/883 Devices

— tpd = 12 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E2CMOS Technology

— 100% Tested

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue Logic and Structured Designs

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER

— PC and UNIX Platforms

FAQ

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