ISPLSI1024-80LJ of Lattice CPLD ispLSI 1000 Family

ISPLSI1024-80LJ FPGAs Overview

The ispLSI 1024 is a High-Density Programmable Logic Device containing 144 Registers，48 Universal I/O pins，six Dedicated Input pins，four Dedicated Clock Input pins and a Global Routing Pool（GRP）.The GRP provides Complete interconnectivity between all of these elements. The ispLSI 1024 features 5-Volt in-system programma bility and in-system diagnostic capabilities.It is the first device which offers non-volatile reprogrammability of the logic，as well as the interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 1024 device is the Generic Logic Block（GLB）.The GLBs are labeledA0，A1.C7（see ISPLSI1024-80LJ Datasheet）.There are a total of 24 GLBs in the ispLSI 1024 device.Each GLB has 18 inputs，a programmable AND/OR/XOR array，and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs.All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.

Features

·HIGH-DENSITY PROGRAMMABLE LOGIC

一High-Speed Global Interconnect
一4000 PLD Gates
一48 I/O Pins，Six Dedicated Inputs
一144 Registers

一 Wide Input Gating for Fast Counters，State Machines，Address Decoders，etc.
一Small Logic Block Size for Fast Random Logic
一Security Cell Prevents Unauthorized Copying

·HIGH PERFORMANCE E2CMOSO TECHNOLOGY

一fmax=90 MHz Maximum Operating Frequency
一fmax=60 MHz for Industrial and Military/883 Devices
一tpd=12 ns Propagation Delay
一TTL Compatible Inputs and Outputs
一Electrically Erasable and Reprogrammable
一Non-Volatile E2CMOS Technology
一100%Tested
·IN-SYSTEM PROGRAMMABLE
一In-System Programmable TM（ISPTM）5-Volt Only
一Increased Manufacturing Yields，Reduced Time-to-Market，and Improved Product Quality
一Reprogram Soidered Devices for Faster Debugging
·COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDS WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
一Complete Programmable Device Can Combine Glue Logic and Structured Designs
—Four Dedicated Clock Input Pins
—Synchronous and Asynchronous Clocks
—Flexible Pin Placement
一Optimized Global Routing Pool Provides Global Interconnectivity
·ispDesignEXPERTTM-LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
一Superior Quality of Results
一Tightly Integrated with Leading CAE Vendor Tools
一Productivity Enhancing Timing Analyzer，Explore Tools，Timing Simulator and ispANALYZERTM

一PC and UNIX Platforms

FAQ

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