ISPLSI1016-80LJNI of Lattice

ISPLSI1016-80LJNI FPGAs Overview

The ispLSI 1016 is a High-Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 1016 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1.. B7 (see ISPLSI1016-80LJNI Datasheet). There are a total of 16 GLBs in the ispLSI 1016 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputsof any other GLB on the device.

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— High-Speed Global Interconnect

— 2000 PLD Gates

— 32 I/O Pins, Four Dedicated Inputs

— 96 Registers

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E2CMOS TECHNOLOGY

— fmax = 110 MHz Maximum Operating Frequency

— fmax = 60 MHz for Industrial and Military/883 Devices

— tpd = 10 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E2CMOS Technology

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue Logic and Structured Designs

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT – LOGIC COMPILER AND COM PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER

— PC and UNIX Platforms

— 100% Tested

FAQ

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